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A DSP Coprocessor for ADSL Lite
Date Issued
1999-01
Date Available
2015-09-25T14:34:18Z
Abstract
This paper presents Massana's DSP co-processor solution – FILU-DMT [1] for enabling soft G.Lite (or ADSL Lite) on Pentium and RISC processors. The user interacts with the coprocessor via a C API which accesses a shared RAM interface. All of the G.Lite DSP functions are pre-programmed and held in ROM. The FILU-DMT is implemented in fully synthesizable Verilog RTL with a single synchronous clock for high scan coverage. It is based on a dual MAC architecture which can perform a radix-4 FFT butterfly in 8 cycles yielding a 256 point FFT in 21 µs. This is the industry's fastest FFT for this class of processor. The FILU-DMT supports block floating-point arithmetic which achieves near floating-point performance at a fraction of the area cost of conventional DSPs.
Type of Material
Conference Publication
Language
English
Status of Item
Peer reviewed
Conference Details
Irish Signals and Systems Conference (ISSC), Galway, Ireland, January, 1999
This item is made available under a Creative Commons License
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