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All-digital RF phase-locked loops exploiting phase prediction
Date Issued
2014-02
Date Available
2017-07-10T15:02:31Z
Abstract
This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC) and to ease the clock retiming circuit. In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation. The presented principles and techniques have been validated through extensive behavioral simulations as well as fabricated IC chips.
Type of Material
Journal Article
Publisher
Information Processing Society of Japan
Journal
IPSJ Transactions on System LSI Design Methodology
Volume
7
Start Page
2
End Page
15
Copyright (Published Version)
2014 Information Processing Society of Japan
Language
English
Status of Item
Peer reviewed
This item is made available under a Creative Commons License
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0
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