Electrical and Electronic Engineering Theses

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Browsing Electrical and Electronic Engineering Theses by Issue Date

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  • Publication
    Reactive Power From Distributed Generators : Characterisation and Utilisation of the Resource
    (University College Dublin. School of Electrical, Electronic & Communications Engineering, 2013-09)
    Cuffe, Paul 
    ;
    Keane, Andrew 
    ;
    O'Malley, Mark 
    ;
    Brazil, Thomas J. 
    Both transmission and distribution system operators must increasingly accommodate renewable generators on their respective networks. This presents numerous technical challenges, amongst which is reactive power management. Failure to appropriately manage reactive power can drive up connection costs for new generators, can harm power system voltage security, and can necessitate onerous must-run generation constraints or procurement of costly dedicated reactive power sources. Additionally, transmission and distribution system operators may wish to deploy reactive power in conflicting ways. For instance, the former may stipulate reactive power regimes for distributed generators that minimise connection costs, while the latter may focus on enhancing power system voltage security. Notably, the literature does not offer extensive insight on resolving these objectives, or on the inclusion of distributed reactive power resources into holistic power system operation and planning activities. Three broad research questions emerge: what is the extent of the reactive power resource offered by distributed generators?; how can these resources be included in power system planning?; and how should distributed generators be operated to balance the needs of the distribution and transmission systems? To frame the first problem, a novel recasting of the traditional capability chart is provided. This chart displays the reactive power capability of an entire distribution network, aggregating together the disparate contributions available from the various generators present. This capability chart can be inferred from time series load flow simulations, as the numerous active and reactive power flows calculated at the transmission node imply the underlying relationship. Notably, the range of reactive support available is heavily dependent on the magnitude, and disposition, of active power flows internal to the distribution network. A more rigorous treatment of these effects demands novel optimal power flow techniques. These techniques deploy non-linear programming in an atypical role, functioning as a search technique to find network operating points that are not optimal in the conventional sense of desirability, but rather indicate the extent to which network conditions may align to hinder reactive support provision. Such aggregate capability charts facilitate novel transmission system reactive power planning techniques. These techniques employ a delineation of how much reactive power will be required by a test generator, which may represent a collection of distributed generators, to adequately control the voltage at its connection node. This requirement varies as the generated active power rises, due to displacement of other generators as well as altered network flows. At each transmission system node, the reactive power requirements can be compared to the capability chart which shows the reactive power availability from the various locally available sources, so deficits can easily be identified. Time series validations demonstrate this planning technique to be usefully predicative in anticipating voltage control problems. Finally, it is apposite to examine how the capabilities of distributed generators may best be harnessed. Further enhancements to the optimal power flow tool become essential here. A tailored implementation of a terminal voltage control mode for distribution generators permits the inclusion of generator voltage control settings as free variables within the optimization framework, whose optimal selection presents many exciting potentialities. The optimal power flow framework must be extended to ensure the suitability of the optimized settings across the full gamut of load and generation conditions that may arise. New objective functions are thus made tractable. Notably, it is possible to maximise the voltage responsiveness of a distribution network, such that a decline in transmission system voltage is met by an injection of reactive power, absent of any supervisory control. Under this scheme, the transformer is locked at an optimized static tap setting which exposes the distributed generators to the voltage fluctuations arising at the transmission level, thus invoking a coherent reactive power response.
      1606
  • Publication
    Advanced distribution network modelling with distributed energy resources
    (University College Dublin. School of Electrical and Electronic Engineering  , 2015)
    O'Connell, Alison 
    The addition of new distributed energy resources, such as electric vehicles, photovoltaics, and storage, to low voltage distribution networks means that these networks will undergo major changes in the future. Traditionally, distribution systems would have been a passive part of the wider power system, delivering electricity to the customer and not needing much control or management. However, the introduction of these new technologies may cause unforeseen issues for distribution networks, due to the fact that they were not considered when the networks were originally designed.This thesis examines different types of technologies that may begin to emerge on distribution systems, as well as the resulting challenges that they may impose. Three-phase models of distribution networks are developed and subsequently utilised as test cases. Various management strategies are devised for the purposes of controlling distributed resources from a distribution network perspective. The aim of the management strategies is to mitigate those issues that distributed resources may cause, while also keeping customers' preferences in mind.A rolling optimisation formulation is proposed as an operational tool which can manage distributed resources, while also accounting for the uncertainties that these resources may present. Network sensitivities for a particular feeder are extracted from a three-phase load flow methodology and incorporated into an optimisation. Electric vehicles are the focus of the work, although the method could be applied to other types of resources. The aim is to minimise the cost of electric vehicle charging over a 24-hour time horizon by controlling the charge rates and timings of the vehicles. The results demonstrate the advantage that controlled EV charging can have over an uncontrolled case, as well as the benefits provided by the rolling formulation and updated inputs in terms of cost and energy delivered to customers.Building upon the rolling optimisation, a three-phase optimal power flow method is developed. The formulation has the capability to provide optimal solutions for distribution system control variables, for a chosen objective function, subject to required constraints. It can, therefore, be utilised for numerous technologies and applications. The three-phase optimal power flow is employed to manage various distributed resources, such as photovoltaics and storage, as well as distribution equipment, including tap changers and switches. The flexibility of the methodology allows it to be applied in both an operational and a planning capacity.The three-phase optimal power flow is employed in an operational planning capacity to determine volt-var curves for distributed photovoltaic inverters. The formulation finds optimal reactive power settings for a number of load and solar scenarios and uses these reactive power points to create volt-var curves. Volt-var curves are determined for 10 PV systems on a test feeder. A universal curve is also determined which is applicable to all inverters. The curves are validated by testing them in a power flow setting over a 24-hour test period. The curves are shown to provide advantages to the feeder in terms of reduction of voltage deviations and unbalance, with the individual curves proving to be more effective. It is also shown that adding a new PV system to the feeder only requires analysis for that system.In order to represent the uncertainties that inherently occur on distribution systems, an information gap decision theory method is also proposed and integrated into the three-phase optimal power flow formulation. This allows for robust network decisions to be made using only an initial prediction for what the uncertain parameter will be. The work determines tap and switch settings for a test network with demand being treated as uncertain. The aim is to keep losses below a predefined acceptable value. The results provide the decision maker with the maximum possible variation in demand for a given acceptable variation in the losses. A validation is performed with the resulting tap and switch settings being implemented, and shows that the control decisions provided by the formulation keep losses below the acceptable value while adhering to the limits imposed by the network.
      433
  • Publication
    Power system planning for high renewables penetration: voltage stability and system frequency aspects
    (University College Dublin. School of Electrical and Electronic Engineering  , 2016)
    Bakhtvar, Mostafa 
    ;
    Keane, Andrew 
    The installed capacity and the grid access request for renewables is anticipated to continue rising in the EU and US in the coming years. The scarcity of reactive power and synchronous inertia are two inherent consequences of high penetration of renewables in the power system. This raises voltage security concerns, and may endanger rotor angle and frequency stability. In order to foresee these challenges, it is essential to carry out extensive planning and operation studies. Thus, new methodologies and innovative metrics are required to ensure secure and reliable operation of power systems.In this thesis, a multi-operating condition AC voltage stability constraint optimal power flow framework has been presented for transmission system planning. This framework captures multiple wind and demand operating conditions within an optimal power flow tool. The voltage stability constrained optimal power flow was applied to wind capacity allocation. It was shown that the capacity allocation pattern affects steady state voltage stability and the total allocated wind capacity. This indicates that a well-chosen allocation of wind capacity is not only in line with the trend of renewables integration in power systems but also enables limiting the occurrence probability of insecure operating points that may require costly remedies.A procedure for wind capacity allocation has been presented based on the finding on the effects of the pattern of wind capacity allocation on voltage stability. This benefits from the potential of an optimal wind capacity allocation for enhancing the voltage stability margin. Unit commitment was employed to take into account the reduction of the available reactive power sources at each operating condition for wind capacity allocation. By setting the wind capacity target and tracking the loadability margin, it was shown how the risk for a reduction in loadability margin may increase with allocation of wind generation. This procedure showed that specific locations in the system are favored for capacity allocation. It also identified weak areas in the network that experience a reduction in the loadability margin as a result of the allocation of the wind capacity. The methodology can help system operators prioritize network access and investment in the network to enhance the integration of renewables.Further, this thesis focused on the power system frequency aspect of renewables integration. Synchronous inertia acts as a means of immediate frequency support in power imbalances. Renewables often inject power into the network through power electronic converters. As such, synchronizing torque and synchronous inertia are not available in the power from renewables. Reduced levels of synchronizing torque raise concerns on rotor speed behavior under power imbalance events. The interaction of generators has been investigated by deriving the synchronizing torque coefficient matrix from the multi-machine Heffron-Philips model. It was shown that the reactive power output of the generators can be used to control the elements of the synchronizing torque coefficient matrix. It was identified that the varying levels of synchronizing torque affect the rate of change rotor speed of generators following a loss of generation event. Furthermore, the effect of rotor speed deviation due to synchronizing torque was presented from the system frequency perspective. This provides a foundation for system operators to establish strategies that benefit from the synchronizing torque coefficient matrix characteristics for controlling the frequency behavior.
      529
  • Publication
    Design considerations for a high power, medium frequency transformer for a DC-DC converter stage of a solid state transformer
    (University College Dublin. School of Electrical and Electronic Engineering  , 2016)
    Mumuluh, Roland Nshieteh 
    ii. ABSTRACTIn recent years, the solid state transformer concept has challenged the conventional low frequency transformer. The conventional transformer cannot store energy and its output is easily distorted as a result of perturbations at its input. In same manner, disturbances from the output unit such as harmonics along with reactive power, as well as load transients are reflected back to the input of the conventional transformer. The size of the low frequency transformer is significantly larger. The Solid state transformer challenges the traditional low frequency transformer in that it eradicates the aforementioned drawbacks and provides multifunctional features.In this thesis a reliable model to design and optimize a high power medium frequency transformer for a dc-dc converter that forms part of a solid state transformer is researched and established. The aim is to use this model to investigate how high can be the operating frequency for a medium frequency transformer to achieve maximum efficiency and minimum volume. The dc-dc converter consists of a transformer that provides isolation between a medium-voltage circuit and a low-voltage circuit in a distribution system, and power semiconductor devices. Transformer operation at medium frequency reduces size and volume due to the inverse relationship of transformer area product and frequency. However, at medium frequency, the transformer is less efficient as a result of increased losses due to skin and proximity effects and the temperature rise constraint. Unlike low power magnetic cores where there are standard sizes and dimensions, high power magnetic cores for medium frequency maybe designed depending on demand or in certain cases, using limited dimensional references. Thus, an optimised transformer design for high power medium frequency relies on how its dimensions are defined. The characteristics expected of a core material for high power medium frequency are that it should have a high saturation flux density; low core loss and the material should continuously operate at high temperatures. The findings revealed that the frequency can be as high as 10 kHz to achieve maximum efficiency and minimum volume. An optimum design depends upon the flux density, the winding current density, the numbers of primary turns, the operating frequency and the power level of the transformer. There is no point operating above 20 kHz as there is very little reduction in volume and the winding loss results to increased temperature and reduces the efficiency of the transformer.
      1335
  • Publication
    Collaborative and Context-Aware Applications for Intelligent and Green Transportation
    (2018-12-06)
    Gu, Yingqi 
    In this thesis, we present several context-aware and collaborative applications of electric and plug-in hybrid vehicles in the context of intelligent transportation systems, with a main focus on the design of control and optimisation algorithms to maximise the performance of such vehicles in different practical scenarios. This gives rise to four topics to be discussed in the thesis. The first topic focuses on the design of speed advisory systems for different road users. In Chapter 3, we present a framework for minimising the energy consumptions for a group of electric vehicles in a distributed manner. Using this framework, we extend the ideas of this design to the case of cyclists, where now we maximise the overall health benefits for a group of cyclists sharing a common route. In both cases, we apply a recently derived consensus mathematical result for solving both convex and quasi-convex optimisation problems with consensus constraints. The efficacy of our proposed algorithm is verified through many simulation studies. The second topic is concerned with a new design of the energy management system for plug-in hybrid electric vehicles (PHEVs) by taking into account the availability of the upcoming renewable energy generation. In Chapter 4, we introduce distributed algorithms for PHEVs to switch on/off their electric motors such that some utility functions can be maximised while achieving a demand and supply balance for power grids when vehicles travel back for recharging. This idea is then extended for the case of plug-in hybrid electric buses (PHEBs) in Chapter 5, focusing on maximising the environmental benefits of buses with some energy constraints to be satisfied. The third topic introduces a novel context-aware engine management system for PHEVs to optimally orchestrate switching between different operational modes so that the environmental benefits on pedestrians can be reached to a maximum. In Chapter 6, we present details of our design for such a system taking account of many factors in practice. We implement the proposed system in a hardware-in-the-loop platform, embedded with a real PHEV, to illustrate the efficacy of our proposed approach. The last topic investigates the ability of simple macroscopic information to identify changes in nominal urban traffic flows. In Chapter 7, we focus on using junction turning probabilities to infer the occurrence of anomalies in traffic patterns. Finally, several simulation studies are conducted in a popular mobility simulator to demonstrate the capabilities of our proposed method.
      917
  • Publication
    Time domain converters and ultra-low-power all-digital phase-locked-loop
    (2019)
    Chen, Peng 
    Internet-of-Things promise the devices the ability to connect, collect and exchange data with little or no human-to-human or human-to-computer intervention. The continued demand for low cost and low power of wireless communications drive research that explores new architectures and techniques in the RF front-end. Time-domain operations are favored by the technology scaling, thanks to the steeper and steeper transition edges having the ability to carry information. Two fundamental time-domain data converters are time-to-digital converter (TDC) and digital-to-time converter (DTC). First, a novel discharging constant-slope DTC is proposed, consuming merely 31 μW running at 40 MHz. Taking advantage of the constant-slope operation, it achieves 1.07 LSB in a 9-bit implementation with a typical resolution of 148 fs. This work also uncovers for the first time two effects that are compensating each other: channel length modulation is compensated by the ramp node varactor. Compared with other constant-slope DTC counterparts and other DTC architectures, the proposed work achieves an outstanding performance. Then, the other basic time-domain block, time-to-digital converter, is introduced thoroughly in the introduction chapter with popular TDC architectures investigated and summarized. The proposed TDC work targets built-in-self-test applications. With the help of the proposed system self-calibration method, the non-ideal effects of analog blocks can be calibrated in a digital manner. The system achieves pico-second level precision with a low-quality clock available in the SoC environment. Two all-digital phase-locked-loops are designed with different applications and techniques. The first one utilizes a ΣΔ technique to dither the DTC control codes to suppress fractional spurs. In the mm-wave applications, it achieves around -30 dBc fractional spur at 60 GHz output. With the help of low noise contribution from the DTC and narrow TDC range benefited from Vernier architecture, the PLL achieves 213{277 fs RMS jitter in 57.5{67.2 GHz tuning range while consuming only 40mW. The second one is applied in the Bluetooth low energy applications. It pursues low power consumption for the PLL so that the battery life can be extended for the radios. With the help of the improved constant-slope DTC and hybrid TDC, together with an optimized low power inverse-class- F VCO, the PLL achieves sub-half-mW power consumption with 1 ps RMS jitter.
      422
  • Publication
    BLE Transceiver/4G Mobile PLL for Wireless Applications
    (2019-01)
    Kuo, Feng-Wei 
    The Internet of Things (IoT) and cellular (mobile) systems are the most promising technologies of the next Fifth Generation (5G) of the mobile broadband network. The radio technological revolution for wireless communications has already begun. In the past, IoT wireless communications have been used in many industries, and a variety of new applications have been developed. As a result, the next-generation wireless technology, popularly known as 5G, promises to deliver new levels of capability and efficiency by supporting a diverse range of future applications, which can change the way we live, work, and communicate with each other. Based on the future 5G applications, this thesis is composed of 5 parts. The first objective of this thesis is to introduce the demands placed on monolithic local oscillators (LO), realized as RF phase-locked loops (PLLs), which are particularly exacting, especially with regard to their integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLL has become a challenging task. For instance, narrow bandwidth systems, such as the GSM of 2G and the enhanced data rate for the WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand particularly low in-band (IB) PN in a mobile cellular system. However, there has arisen a new class of operation for RF oscillators and 2-way parallelism of TDC with PVT stabilization to fill the performance/power gap in the ultra-high figure of merit (FoM) and ultra-low phase noise space. The proposed oscillator and TDC should also be implemented as the heart of a PLL system to demonstrate their superiority in a real implementation. The second objective of this thesis is to introduce an all-digital PLL that employs a digitally controlled oscillator (DCO) with switching current sources to reduce the supply voltage and power without sacrificing its phase noise and start-up margins. The DCO also reduces its 1/f noise, allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during direct DCO data modulation. The switching power amplifier (PA) integrates its matching network while operating in class E/F2 to maximally enhance its efficiency. The transmitter is realized in 28-nm CMOS and satisfies all metal density and other manufacturing rules. Another system-level approach is to develop the first ever fully discrete-time superheterodyne receiver for IoT applications, such as Bluetooth low-energy (BLE). It exploits the fast switching speed and low internal capacitances of deep-nanoscale CMOS devices to realize a high intermediate-frequency (IF) architecture based on switchedcapacitor- based charge-domain bandpass filtering. The power consumption is minimized by aggressively reducing the size of the MOS devices and judiciously applying a sampling-rate decimation. The resultant increase in flicker noise is mitigated by placing the IF frequency beyond the flicker corner frequency. Likewise, the decimation-induced aliasing is mitigated by DT filtering of preceding stages. To improve the power efficiency of a Bluetooth low energy transceiver by exploiting a novel digitally controlled oscillator, a class E/F2 switched-mode PA and a new discrete-time (DT) receiver (RX) are adapted to achieve high out-of-band linearity, low noise and low power consumption. In addition, an integrated on-chip matching network serves both the PA and LNTA, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The third objective of this thesis is to introduce an ultra-low voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5V supply. While its DCO runs directly at 0.5 V, an internal switched-capacitor DC–DC converter ‘doubles’ the supply voltage to all the digital circuitry and particularly regulates the TDC supply to stabilize its resolution, thus maintaining fixed in-band phase noise across process, voltage and temperature (PVT) variation. Moreover, the impact of voltage supply scaling on the power consumption and performance of a discrete-time (DT) superheterodyne receiver (RX) for IoT applications and realized in deep nanoscale CMOS using inverter-based gm and switched capacitors has been studied. The power supply is partitioned into three separate domains: RF, IF processing, and clocking, which allows them to be independently regulated to assess their respective impacts. The DT-RX maintains its functionality, albeit with some acceptable loss of performance, when the core supplies are varied by as much as an octave, i.e. from the nominal 1.1V down to 0.55 V. The DT-RX IC is then connected to a switched-capacitor based voltage doubler array on a companion IC die such that the DT-RX can be powered at the octave range of 0.275–0.55V from an energy harvester. The sensitivity at the doubler’s 0.275/0.55V input is -85/-95dBm while consuming 1.0/2.4mW. The fourth objective of this thesis is to introduce a sub-GHz transmitter (TX) with a physically merged DCO and digital power amplifier (DPA). The matching transformer of single-ended DPA is placed inside the DCO transformer to save c. 50% of area. The resulting DCO pulling is compensated via a feedback path and an inter-winding cancellation capacitor suppresses the 2nd harmonic. Fabricated in 16-nm FinFET CMOS, the DPA reaches 51% efficiency at 11dBm output with <-55 dBc second harmonic (HD2). The fifth objective of this thesis is to improve the power efficiency and frequency range of a dual-frequency-band radar system by exploiting a third-harmonic boosting DCO simultaneously generating 22.5–28GHz and sufficiently strong 68–84 GHz signals to satisfy short-range radar and medium/long range radar requirements.
      2615
  • Publication
    Flicker Noise Upconversion and Reduction Mechanisms in RF/Millimeter-Wave Oscillators for 5G Communications
    (2019-09-19)
    Hu, Yizhe 
    The fifth generation (5G) cellular communications in millimeter-wave (mmW) bands (e.g., 28GHz) place very tough requirements on phase noise (PN) of local oscillators (LO). However, in the advanced CMOS technology (e.g., 28nm, 16nm, 7nm, ...), the intrinsic 1/f current noise of MOS transistor is increasingly worsening. It could adversely affect the PN of the LO significantly, especially the flicker PN, leading to a very high 1/f3 PN corner (usually exceeding 1 MHz), which is difficult to be attenuated by a mmW PLL. On the other hand, the current literature is full of conflicts and confusing theories about the flicker noise upconversion, with a large number of ambiguities in the RF range, let alone in the mmW range. Thus, lowering the 1/f3 PN and figuring out its actual mechanisms are highly desired for 5G mmW communications.
      977
  • Publication
    Fully Integrated Switched-Capacitor DC-DC Converter in All-Digital PLL for IoT Applications
    (University College Dublin. School of Electrical and Electronic Engineering, 2019-11-19)
    Pourmousavian, Naser 
    The development of Internet of Things (IoT) is driving research and innovation to connect our day-to-day ‘things’, such as wearable devices, wireless electronics, implantable sensors, and smart appliances. The ‘smart’ nodes in IoT applications generally comprise wireless communication blocks, power management units (PMUs), energy sources, digital signal processing, and sensors, and are often implemented as system-on-chip (SoC) solutions. Consequently, high power efficiency, low power consumption, small silicon area, and low cost are the main requirements for IoT SoC implementation. Several popular standards, such as Bluetooth low energy (BLE), are defined for IoT. The development of radios for IoT node devices has spurred research in ultra-low-power (ULP) all-digital phase-locked loops (ADPLLs) performing as local oscillators (LOs). The IoT concept entails stringent conditions on the size and weight of the battery. In spite of recent advancements, the IoT system lifetime is still limited by the power consumption of its radio, and in particular the LO. Consequently, this triggers inconvenient battery replacements, which limits their marketing attractiveness. The lifetime could be easily extended with larger batteries but that comes at a price of increased weight and size and it is clearly against the vision of IoT miniaturization. Energy harvesters can significantly extend the IoT lifetime up to the point of perpetual operation. Among them, solar cells have gained a significant popularity due to their high-power density and low cost. However, they typically provide low voltages, especially when operating indoors, often well below the typical supply of CMOS circuits. This is likely to degrade performance of important ADPLL building blocks. An inverter-based time-to-digital converter (TDC) is such an example. In this dissertation, we carry out research to implement an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5V supply which has never been done before. We demonstrate that while its digitally controlled oscillator (DCO) can run directly at 0.5 V, an internal switched-capacitor dc–dc converter could be employed to ‘double’ the supply voltage to all the digital circuitry and particularly to regulate the TDC supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage and temperature (PVT). The ADPLL supports 2-point modulation and forms a BLE transmitter realized in 28-nm CMOS. It maintains excellent in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86 ps while dissipating only 1.6mW at 40MHz reference. The power consumption reduces to 0.8mW during the BLE transmission when the DCO switches to open-loop. Furthermore, to go towards even lower voltages, we implement the first-ever deep sub-1V monolithic step-up dc–dc converter operating at 0.18–0.4V that outputs significant power for IoT with a peak power efficiency of 81.2% at 50 µW output power for the 0.18V input, and 87.1% at 300 µW output power for 0.4 V. It is implemented in 16-nm FinFET CMOS and uses a metal-oxide-semiconductor (MOS) transistor as a high-density flying capacitor for energy conversion. The capacitor is arranged in a self-biased deep N-well topology, which enhances the overall efficiency by 9.5%. An integrated time-to-digital converter (TDC) verifies the dc–dc output quality.
      788
  • Publication
    A Circuit Design Journey from Room Temperature to Cryo Temperature
    (University College Dublin. School of Electrical and Electronic Engineering, 2020)
    Esmailiyan, Ali 
    The continual advancement of CMOS technology results in faster and more power efficient digital processing. Concurrently, the supply voltage of CMOS circuits is scaled lower and this leads to smaller voltage headroom, which raises challenges in designing analog circuits with every new CMOS technology node. To overcome these challenges, there have been significant interests in time-based analog-todigital converters (ADCs). To convert an input voltage signal to time domain, some kind of voltage-to-time conversion (VTC) is needed. The linearity of this VTC usually limits the performance of time-based ADCs. To solve these problems, this thesis proposes and realizes in TSMC 28-nm CMOS two new techniques in the time-based ADCs using a VTC. In the first design, the proposed ultra-low-voltage ADC makes use of a Dickson charge pump circuit (Dickson CP) as part of VTC to convert the input analog voltage into time domain by modulating the slope of the ramp. In the second design, to compensate the nonlinearity in the generated ramp signal from the Dickson CP, a digital compensation scheme is proposed. As the Moore’s law of scaling of transistors is losing its momentum, there have been significant interests aiming to extend the exponential growth in computing power by means of “quantum computing", which promises to solve sophisticated and currently intractable problems in various applications, such as simulation of chemical reactions, modeling financial transactions, finding cure for COVID-19, etc. In order to control the extremely fragile quantum bits (qubits) with an accurate manipulation and readout, the quantum computers also require extremely low (cryogenic) temperatures to operate so as to preserve their coherent superposition state. The second part of this thesis presents an interface circuitry which is located on the same die and close to the quantum experiment cell. This includes key building blocks, such as digital-to-analog converters (DAC) and detectors. The proposed circuits are designed to operate at cryogenic temperatures around 4 K. They are implemented in 22-nm FDSOI CMOS from GlobalFoundries. Cryogenic test setup and off-chip controlling circuits are also presented.
      116
  • Publication
    Frequency Control of Distributed Energy Resources Integrated into Low Voltage Distribution Network
    (University College Dublin. School of Electrical and Electronic Engineering, 2020)
    Ibrahim, Ismail 
    ;
    0000-0002-6744-8227
    The growth in the integration of converter interfaced renewable energy has reduced the system inertia, which threatens system stability due to high rate of change of frequency and frequency nadir issues unless steps are taken to mitigate it. There is a need to provide sufficient fast frequency response to maintain adequate inertia in the system. This thesis investigates the capabilities of a large population of distributed energy resources such as residential energy storage and heating loads to provide an emulated inertial response. There is a need to find improved ways to analyze, test and evaluate the new control strategies for the provision of inertial response. Real-time simulation with hardware in the loop provides a very promising approach for this which enables the coupling of real hardware with power system simulations thus enabling study of the real-time interactions between the hardware and control and the wider system. This thesis presents a real-time simulation platform with hardware in the loop aimed at providing a platform for the test and evaluation of new technologies and new control strategies for the integration of distributed energy resources. The distribution grid model used for the real-time simulation is based on distribution grid in the Manchester area. This network contains three feeders with 330 houses, 6350 nodes and three-phase, four-wire configuration distribution cables. The conventional on/off controlled demand response, when installed in a large number of loads require some coordination for stable operation of the power system. Also, it is not possible to incorporate inertia emulation techniques into the on-off controlled demand response. This thesis proposes an inertial emulation technique for heating loads, both resistive loads and heat pumps. The thesis presents the small-signal transfer functions, stability analysis, and aggregated response of a large population of virtual inertia controlled resistive heaters and heat pumps. Finally, the thesis presents an investigation of the control based on grid-following and grid-forming approach for a single-phase residential battery storage system for the provision of frequency support. The thesis presents the full switched, reduced order model and small-signal transfer function for single-phase grid following and grid forming energy storage converters with virtual inertia control. Then the thesis presents stability analysis and simulations of a large population of energy storage converters in the real-time simulation platform. There are no stability issues with the grid-following approach, but the grid forming approach has more limited stability range. The simulation results shows the interaction between frequency support with voltage, and the effect of controller settings on voltage and frequency support.
      92
  • Publication
    Merging of RF Oscillator and Power Amplifier to Enable Fully Integrated Transmitters for Internet-of-Things
    (2020)
    Xu, Kai 
    To facilitate the ever-increasing influx of the Internet-of-Things (IoT) wireless connectivity, the investigation for power efficient and cost effective wireless devices together with the trend towards fully integrated solutions have opened up a new wave of challenges and opportunities for ultra-low-power (ULP) RF integrated circuit design. The full integration of the power- hungry battery-operated CMOS transmitter (TX) is especially challenging and confronted by the down-scaled power supply, lossy on-chip passives and low-resistivity silicon substrate of nanoscale CMOS technology. This sets different requirements for devices working in different RF bands, mainly the 900 MHz (sub-GHz) and 2.4 GHz bands in terms of range coverage, data rate, maximum allowed RF power, etc. Specifically, the Bluetooth Low Energy (BLE) as the mainstream standard for IoT applications in that the 2.4 GHz band is constrained by the transmitter system efficiency ?TX due to the fact the power dissipated by the modulator PDC,MOD is generally comparable or even higher compared to the delivered RF power PRF by the power amplifier (PA). Furthermore, PDC,MOD cannot scale down when the PA operates at large power back-off. On the other hand, the 802.11ah, or equivalently WiFi-HaLow, sits in the 900 MHz (sub-GHz) band targeted for long-range wireless connectivity which faces the greatest challenge of inexpensively integrating the RF passive components, especially inductors and transformers utilized for frequency generation or impedance matching. In this thesis, we propose to merge the oscillator (the most power-hungry block in the modulator) and the power amplifier either in the way of “functionally merged” DCO-PA for BLE transmitters in order to boost the system efficiency at large power back-off or in the way of “physically merged” DCO-DPA for WiFi-HaLow transmitters to tremendously reduce the die area. One chip prototype is fabricated to demonstrate the sub-GHz 802.11ah transmitter (TX) with a physically merged digitally controlled oscillator (DCO) and digital power amplifier (DPA) saving ~50% of area. The resulting DCO pulling by the DPA is compensated via a feedback path and an inter-winding cancellation capacitor suppresses the 2nd harmonic. Further, we introduce a super-simple RF front-end with a fully integrated matching network for 2.4 GHz TDD radios featuring a functionally-merged single-MOS DCO-PA and a zero-shifting capacitor that suppresses the 2nd harmonic emission. This not only allows to share the same antenna pin with the RX but also provides passive-gain boosting to an RX low noise amplifier (LNA).
      575
  • Publication
    Low-Power Analog-to-Digital Converters in Nanometer CMOS for IoT Applications
    (University College Dublin. School of Electrical and Electronic Engineering, 2020-03-26)
    Wang, Hongying 
    The ever increasing demands for Internet-of-Things (IoT) networks promote the trend of power-efficient system design at the analog front-end, analog-to-digital converter (ADC), RF transmitter (TX) and digital signal processing (DSP) levels. This is further motivated by the relatively slow development in power storage technology and consumer expectations of long operational and stand-by times. To achieve inexpensive large-scale integration while exploiting improved digital power efficiency, IoT networks are preferably realized in a deep nanoscale CMOS technology. However, it is rather challenging and power-consuming to implement high-performance continuous-time (CT) amplifiers and comparators, which generally are indispensable elements for most conventional ADCs in deep nanometer CMOS given the low intrinsic gain of transistors and reduced supply voltage; therefore, passive and digitally intensive ADC topologies are attractive alternatives in deep nanometer CMOS to improve power efficiency. For applications demanding high resolution and good linearity, Delta-Sigma ADCs can be a suitable option since they can relax front-end anti-aliasing filtering and suppress in-band quantization noise by oversampling and noise-shaping techniques. To promote low power, passive integrators containing only switches and capacitors can be adopted. In this thesis, we demonstrate a passive switched-capacitor (sw-cap) modulator based on pipelined charge-sharing rotation in 28 nm CMOS, which not only eliminates any inter-stage loading effects that plague the conventional sw-cap passive modulators, but also relaxes settling requirements and improves power efficiency. For applications dealing with sparse signals and demanding low-medium resolution and compressed output data size, level-crossing (LC) ADCs can be a good option since they can produce an input-dependent average sampling rate, thus reducing the power consumption of the RF TX and DSP for data transmission and processing, respectively. In this thesis, we introduce a digitally intensive event-driven quasi-level-crossing (quasi-LC) delta-modulator ADC with an adaptive-resolution (AR) algorithm. The proposed AR quasi-LC delta modulator quantizes the residue voltage signal with a residue quantizer, which enables a straightforward implementation of LC and AR algorithms in the digital domain. The proposed modulator achieves data compression by means of a globally signal-dependent average sampling rate and achieves adaptive resolution through a digital multi-level comparison window which overcomes the trade-off between the dynamic range (DR) and input bandwidth as presented in conventional LC ADCs. The residue quantizer is firstly implemented as a Successive-Approximation-Register (SAR) sub-ADC for better power efficiency, and then it is also implemented as a voltage-controlled-oscillator (VCO)-based sub-ADC to achieve higher DR and average sampling rate for low-amplitude and slowly-varying signals.
      511
  • Publication
    Modeling and Stability Analysis of Power Systems with Discontinuous Right Hand Side Differential, Algebraic Equations
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Murad, Mohammed Ahsan Adib 
    ;
    0000-0002-5832-2980
    Power systems are one of the most complex dynamic systems due to their multi-time scale and non-linear nature. This work focuses in particular on the electromechanical dynamics of power systems which are hybrid (discrete-continuous) and are therefore studied using a set of Hybrid Differential-Algebraic Equations (HDAEs) or Discontinuous Right-Hand Side DAEs (DRHS DAEs). Traditional HDAEs possess several challenges during modeling, implementation, and numerical simulation stages, depending on the nature of the discontinuities arising from different applications. This thesis studies the impact of discontinuities on power system physical stability as well as on the numerical stability of a solver considering two specific discontinuous models. The first model is an under load tap changing transformer, which introduces a discrete variable in the DRHS DAEs due to the physical operation of the transformer. The second model is a proportional-integral controller used in different components of power systems, e.g. voltage source converter and automatic voltage regulators which introduces a discontinuity in the state and algebraic variables of DRHS DAEs. In particular, a thorough discussion of the deadlock and chattering issues during time-domain simulation arise from the latter model is provided. This discussion is based on two time domain simulation techniques widely used in power system tools, namely, time-stepping and event-driven method. To solve the deadlock and chattering issues in both of these simulation techniques, a theoretical approach given by Filippov is proposed. Case studies with small to large sizes, e.g., single machine infinite bus, WSCC 9-bus, IEEE 14-bus, 74-bus Nordic system and all-island Irish system with 1479-buses connected to a simplified 63-bus Great Britain system through a high-voltage direct current link are considered and tested in the thesis. Simulation results indicate the importance of accurate modeling and implementation of discontinuous models for dynamic analysis.
      167
  • Publication
    Broadband radio frequency power amplifiers for 5G wireless communications
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Xu, Y. (Yang) 
    ;
    0000-0001-6252-6997
    Power amplifier (PA) is one of the key components in radio frequency (RF) front-end transceiver and its performance has a critical impact on wireless systems. In the coming fifth-generation (5G) wireless telecommunication system, due to the growing data traffic, there are increasing demands for higher data rate, wider bandwidth and higher spectrum efficiency. Moreover, modulated signals with high peak-to-average power ratio (PAPR) are widely adopted in 5G systems, requiring PAs to provide high power dynamic range. In this thesis, PA design methodologies aiming at performance enhancement with respect to bandwidth, efficiency, linearity and power dynamic range are comprehensively discussed under 5G sub-6 GHz applications. In each topic, both theoretical analysis and circuit verification are provided. Firstly, the broadband solution for maintaining PA's high efficiency is discussed. The broadband continuous mode operation is analyzed. Based on it, a practical design methodology to construct output matching networks for broadband continuous mode PA is proposed. This solution is designed for Monolithic Microwave Integrated Circuit (MMIC) process which enables compact circuit design with high power density. A prototype PA with 0.25 um Gallium Nitride (GaN) MMIC process is implemented. Secondly, in addition to broadband continuous mode PA design, its linearity performance is analyzed. The simulation reveals that the linearity behaviour varies with frequency inside the extended impedance space provided by continuous mode. To unify the linearity in broadband, a circuit level linearity compensation method adopting clipping contours is presented. A design example implemented with 0.25 um GaN HEMT is demonstrated to validate the method. Thirdly, the bandwidth and efficiency performance at output power back-off is investigated. A design methodology for the broadband Doherty power amplifier (DPA) is presented. To extend the bandwidth and output power back-off range simultaneously, a modified load modulation network is proposed. Based on the analysis and case studies, a series of generalized formulas for estimating design parameters are then introduced, offering broadband solution for arbitrary current ratio and power back-off. A prototype DPA is demonstrated and implemented with packaged GaN devices using proposed formulas. The last part proposes another design methodology for enhancing efficiency at output power back-off. A new way of load modulation is realized with a three-stage load modulated power amplifier architecture. This new load modulation mechanism enables flexible output power back-off and efficiency enhancement within large power dynamic range. Under the proposed architecture, the power back-off can be reconfigured without redesigning the circuit.
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  • Publication
    A Vertically Integrated RFDAC with Analog Linear Interpolation in 28-nm CMOS
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Zhang, Feifei 
    Wireless systems in high data-rate applications, such as cell phones, laptops as well as small base stations, are increasingly required to support wide signal bandwidth and complex modulation schemes. At the same time, they are pushed towards higher levels of system integration and smaller silicon die area for the sake of cost. The demands of transmitting wideband signals have created plenty of challenges to the digital signal processor (DSP) in the transmitter. In DSP, the baseband signals are generated and up-sampled to higher bandwidths and sampling rates. The digital filter used in the up-sampling process should have a certain order and speed determined by the system specifications. As wideband baseband signals become popular in emerging applications, high-order and high-speed digital filters are required, increasing the complexity and power consumption of DSP. It motivates us to consider whether the complex digital processing can be partially done by on the other, i.e., or non-DSP side or “radio frequency” side, as the high frequency carrier already exists in the RF domain and it can be potentially used for baseband signal processing. As one of the key blocks in a communication system, the conventional transmitter comprises a considerable mount of analog circuits, such as the digital-to-analog converter, the low-pass filter, and the RF modulator. Firstly, these analog blocks are sensitive to the environment. Therefore, careful attention is required during the layout. Secondly, it is usually unavoidable to redesign these analog blocks when the system specifications are modified. These features constrain the transmitter to fully take advantage of the advanced CMOS technology. Alternatively, the radio-frequency digital-to-analog converter (RFDAC) which contains the all-digital modulator and digitally controlled power amplifier (PA) can fully take advantage of the technology scaling and robustness of the digital circuits. In this thesis, a vertically integrated RFDAC is proposed and implemented. As the RFDAC naturally features the digitally intensive architecture, it demonstrates better reconfigurability, amenability to technology porting, and capability of extensive self-calibration and self-testing. All these features match well with today’s demands for communication systems that are highly integrated, consume little space, and are power efficient. The PA is the key power-hungry building block of the transmitter. Thus, any improvement on its efficiency can significantly benefit the application. Furthermore, to efficiently deliver power to the load, the PA needs at least one matching network, which is composed of transformers, inductors and capacitors. These passive devices occupy large areas on the chip, making the PA the most area hungry and, consequently, the most expensive block of the entire transmitter. This naturally leads to research on how to enhance the PA’s efficiency with smaller area. To align with the all-digital modulator in RFDAC, digitally controlled switch-mode power amplifiers of class-D/E/F are proposed and implemented. To reduce the PA area, a vertical integration approach is proposed, first time ever in an RFDAC. The vertical integration takes advantage of the fact that area-consuming passive components of the matching network, like inductors and transformer, are fabricated in top metal layers. The active blocks can be built with lower metal layers and put underneath of the passive components. As a result, the passive components, which are on-chip yet occupy a significant portion of the area, will not require their dedicated silicon areas, thus leading to a lower silicon manufacturing cost. By far, the vertical integration method has been tried in designs of limited output power, due to the reason that the metal utilization needs to be carefully organized for passive devices including shielding, active circuits, power supply and ground. It is even more challenging for high output power systems, owing to fact that the top metal layers cannot be used for power supply or ground any longer to retain low impedance. This issue should be solved in the scenario of designing a high output power RFDAC by adopting the proposed vertical integration. As the crowning of this research, a wideband 2.4 GHz 2×9-bit Cartesian RFDAC has been successfully demonstrated in TSMC 28-nm LP CMOS. An 8× analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in the digital processing back-end. The multiport transformer is adopted in the matching network to improve the back-off efficiency. The RFDAC operates across the 3-dB bandwidth from 1.8 to 2.8 GHz. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of the measured peak efficiency. Vertical integration is introduced in the physical implementation, where all key active circuitry is located underneath the transformer-based matching network, achieving a core area of merely 0.35 mm2. According to some rough estimates, the core area has been reduced to 60% of the area achieved by adopting the transitional integration method. The vertical integration enables this implemented RFDAC achieving a much smaller area among comparable prior arts.
      437
  • Publication
    BJT Based Precision Voltage Reference in FinFET Technology
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Kamath, Umanath Ramachandra 
    FinFET technology has been widely adopted for high-performance computing chips and large mixed-signal System-on-Chip (SoC). This work addresses the problem of realizing high-precision voltage references in deep nanoscale FinFET process technology. Such a problem requires consideration both at the device and circuit levels as well as their co-optimization. Hence, this thesis begins with a BJT device and its characterization in 7-nm FinFET process followed subsequently by utilizing these constructed device models for circuit realization. This work highlights the BJT device SPICE modeling and characterization results in 7-nm FinFET CMOS technology, giving special emphasis to the BJT’s variability and process spread in order to provide insights into key device-circuit interactions. This guides the optimization choices for the designer, which is crucial for analog design in deep nanoscale CMOS. BJT device characterization in 7-nm FinFET process is essential to enable not only precision voltage references, but also for other circuits such as temperature sensors, current references which use BJT at its core. Besides, the key parameters characterized helps predict the limit of achievable precision due to the underlying device inaccuracy. Subsequently, this achieves the aim of quantifying the system application performance. Measurement results of two test-chip device arrays are presented to demonstrate the feasibility of using BJTs in FinFET CMOS and the associated operating conditions (bias current density) optimal for achieving high-precision circuits. Instead of using the standard BJT layout structure available from the foundry, a merged layout structure was implemented which further saves 20% of the silicon area. This area saving layout of the BJT device could be useful for certain applications such as distributed reference or thermal sensors in large SoC. In the next part of the work, we present a 1-V precision voltage reference with a programmable temperature coefficient (‘temp-co’).The voltage reference is based on a parasitic BJT realized within the process steps available in the chosen 7-nm FinFET technology and characterized in the earlier part of this thesis. The targeted precision for this work was achieved by employing trimming techniques to manage the process spread and using two curvature compensation methods. The architecture together with these techniques ensured that the circuit was capable of handling any variation in the device models since the process technology was not mature at the time of design. In addition, the proposed architecture also is capable to program the ‘temp-co’ which is shown to be beneficial in certain applications, to compensate for any system-level thermal degradation. The reference circuit was implemented in a 7-nm TSMC FinFET technology and achieves a maximum inaccuracy of±0.2% and a minimum temp-co of 6ppm/°C from -45°C to 125°C,which is favourable in comparison to state-of-the-art voltage references. Furthermore, its temp-co is digitally programmable between -7 mV/100°C to +8 mV/100°C using a 7-bit flat-trim control code, which is an additional feature of architecture to cope with thermal gradients across large SoC by compensating system-level performance across temperature. The proposed voltage reference has a line regulation of 0.1%/V, and occupies area of 0.078 mm2.
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  • Publication
    Reference Oversampling for Digital Frequency Synthesis
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Du, Jianglin 
    ;
    0000-0002-4533-3576
    To satisfy the strict ultra-low-power (ULP) requirements of Internet-of-Things (IoT) applications, frequency generators, as one of the most power hungry IoT blocks, must achieve high power efficiency while maintaining low phase noise (PN). The PN of frequency synthesizers is mainly determined by 1) phase detector's (PD) noise affecting in-band, and 2) oscillator's PN affecting out-of-band spectra. Traditional analog charge-pump-based phase-locked loops (PLL) face the performance degradation of PD due to the short-channel effects and limited voltage headroom of transistors in advanced technology. They also suffer from the large area occupied by bulky analog loop filters. All-digital PLLs (ADPLL) are highly compatible with the technology scaling and offer a seamless digitally intensive calibration. However, the limited linearity and resolution of a time-to-digital converter (TDC) degrades the phase noise performance. Targeting the ULP requirements in advanced CMOS technology, an oscillator of high power efficiency, and a PD of ultra-low noise in the fractional-N operation are highly sought candidates to realize RF and mm-wave frequency synthesis of high performance. In this thesis, I first propose a compact ULP 2-2.8 GHz digitally controlled oscillator (DCO), which operates at an ultra-low 0.2-0.3 V supply voltage to support energy harvesting for IoT applications. A new inverse class-F23 operation is demonstrated, which intentionally reduces the harmonics in the waveform to reduce the 1/f noise up-conversion by a proposed high magnetic-coupling (km) transformer. The upconverted phase-noise flicker (1/f3) corner reaches below 100 kHz over a 35% tuning range. Secondly, I introduce a reference-sampling all-digital PLL (RS-ADPLL) avoiding the typical power-hungry low-noise reference buffer to achieve low power and large locking range. The necessarily low time-to-voltage gain during the reference sampling is compensated by a two-stage gated amplifier which also reduces the next stage quantization noise from an ADC. By means of this digitally intensive implementation, the detector offset can be calibrated out in digital blocks. The proposed ADPLL reaches -249 dB FoMjitter with 1.1 mW power consumption. Followed by this work, I demonstrate, for the first time ever, a reference oversampling (ROS) ADPLL supporting fractional-N operation. By using a bottom-plate sampling and common-mode (CM) voltage zero-forcing technique, the proposed PD achieves a 4x reference frequency detection rate to reduce the PD noise and re-locking time under the low-power condition. The fractional-N phase is compensated with capacitive DACs controlled by a sinusoidal look-up-table (LUT) and the same DACs also preset the CM voltage for oversampling to obtain high power efficiency. The proposed 2-2.3 GHz ADPLL achieves -247 dB FoMjitter while only consuming 1.15 mW. Finally, the proposed ROS PD technique is extended to millimeter-wave (mmW) application. A novel 24--31 GHz fractional-N mmW ADPLL is introduced employing the ROS-PD. With the 4x reference frequency operation of the loop, the proposed ROS-ADPLL achieves 237 fs while using a standard 50 MHz reference frequency. Together with the class-F3 oscillator and 3rd harmonic extraction, the whole system consumes 11.5 mW leading to FoMjitter-N of -269.3 dB.
      167
  • Publication
    Modelling and Simulation of Long-Term Dynamics in Power Systems
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Kërçi, Taulant 
    ;
    0000-0003-4748-3399
    A reliable and cost-effective operation of power systems involves different tasks over different time horizons ranging from tens of milliseconds (protection) to years (planning). Generally, power system operators routinely check the effectiveness of these tasks separately (depending on time constants) through computer studies based on mathematical models. While the modelling and simulation of short-term dynamics of power systems (e.g. electromagnetic and transient simulation) have received tremendous attention in the literature, that is not the case for long-term dynamics. In this context, this thesis aims to assist power system operators in addressing the modelling and simulation of long-term dynamics in modern power systems (minutes to years). To do so, the thesis presents novel mathematical and software tools that allow studying the long-term impact interactions between different short-term electricity markets models and power systems, and the impact of energy policy incentives on the evolution of Renewable Energy Sources (RESs) technologies, particularly that of solar Photovoltaics (PVs). Short-term electricity markets are essential tools to guarantee the reliable operation of the power system. They are moving closer to real-time and using finer time resolutions (e.g. 5 minutes) in response to the large-scale integration of variable RESs. This means that their dynamics evolve with a timescale similar to some long-term power system dynamics, e.g. the Automatic Generation Control (AGC). Consequently, assessing the impact interactions between such markets and the dynamic response of the power grid becomes increasingly important. The contributions on this topic are as follows: (i) Investigate the effect of real-time electricity markets modelled as a sort of discrete AGC or Market-based Automatic Generation Control (MAGC) on power system dynamics. In particular, a thorough analysis using Time Domain Simulations (TDSs) is provided. (ii) Propose a short-term dynamic electricity market model that includes the memory effect of market participants. Particularly, the effect of the memory of suppliers on the decision-making (generator schedules) and dynamic response of the grid is discussed. (iii) Investigate the impact interactions between sub-hourly deterministic Unit Commitment (d-UC) and stochastic Unit Commitment (s-UC) and the power grid. Furthermore, the thesis also proposes a dynamic model based on nonlinear delay Differential-Algebraic Equations (DAEs) able to predict the evolution of PV installations for different countries. This model is a valuable tool that can help policymakers in the decision-making process, such as the definition of the Feed-in Tariff (FiT) price and the duration of the incentives. Finally, the proposed models and tools are duly validated throughout the thesis by means of numerical tests based on benchmark test systems.
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  • Publication
    Vision from a brief glimpse: the cognitive role of the lowest level of visual cortical activity
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Mohr, Kieran 
    ;
    0000-0002-6165-7810
    In order to generate the rich experience that is visual perception, the brain must accomplish the impressive feat of transforming a continuous stream of light that arrives at the two-dimensional retinal surface into a coherent three-dimensional representation of the objects, colours and scenes that surround us. Although this appears to us to happen quite automatically and effortlessly, a highly evolved and complex system of neural processes are involved in generating it. We are also not simple passive receivers of visual information but rather actively combine visual input with our past experience to create our perception. This interplay between visual input and past experience can provide a great deal of flexibility to calibrate our perceptual processing in line with our surroundings. In some cases, this can have important implications for our survival as when we mistake a tree root for a dangerous snake on a jungle path whereas we wouldn’t give a second’s notice to the garden hose in our back yard (assuming we are fortunate enough to live in a place where garden snakes are uncommon!). Other times, this flexibility can be used for purely leisurely purposes as when we stare at the sky and pick out images of dogs and elephants in the clouds. Yet while there is clearly a great deal of flexibility in our perceptual apparatus, unfettered flexibility would likely not be very adaptive; while we were caught up in our mind’s eye with whatever fantasy we might wish to behold, we might not notice that we were about to become somebody’s dinner. Therefore, the balance between flexibility and rigidity in our visual system is likely to lie at a point that allows for the generality to recognize objects from many different vantage points and in many different environments without permitting us to get carried away with our imaginations. One proposition has been that there is a certain extent of visual processing that proceeds rigidly, without being amenable to top-down influences, and that lays the foundations and sets the limits for our perception. Anatomically, the visual system is divided up into a large number of distinct processing areas and so one candidate area that could provide such veridical processing of information is area V1, the entry point of visual information to the cortical processing suite. However, investigations of the impact of one avenue of top-down influence (spatially directed attention) have yielded mixed results. Results from animal neurophysiology have demonstrated that V1 responses can be modulated by spatial attention under some circumstances but non-invasive electroencephalography (EEG) in humans has most often failed to detect modulation of V1 responses by spatial attention. By contrast, this thesis will argue that V1 responses in humans are amenable to modulation by spatial attention but that these modulations are nuanced and in order to detect them, careful consideration needs to be given to the choice of task paradigm to account for both V1 response properties and the flexibility of visual attention. It will further argue that V1 responses can directly drive visual perceptions that make use of the visual features that V1 extracts. Finally, EEG measurements are coarse and while there is widespread belief that a particular signal, the C1, reflects activity originating in V1, there have also been challenges to this claim. Thus, this thesis will also provide new evidence in support of the claim that V1 activity is reflected in the C1. Taken together, these findings contend that V1 does not simply extract basic visual features to be passed on to cognitive processes further downstream. Rather, V1 is integrally involved in processes of visual cognition, facilitating goal-driven attentional processes and even directly driving perceptual decisions. This challenges the notion that attentional mechanisms are restrained from altering the earliest stages of visual processing.
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