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- PublicationA 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converterWe propose a 50-MS/s two-step flash-ΔΣ time-todigital converter (TDC) using stable time amplifiers (TAs).The TDC demonstrates low-levels of shaped quantization noise. The system is simulated in 40-nm CMOS and consumes 1.3 mA from a 1.1 V supply. The bandwidth is broadened to Nyquist rate. At frequencies below 25 MHz, the integrated TDC error is as low as 143 fsrms, which is equal to an equivalent TDC resolution of 0.5 ps.
352Scopus© Citations 2 - PublicationA 0.5V 0.5mW switching current source oscillatorThis paper proposes a new RF oscillator topology that is suitable for ultra-low voltage and power applications. By employing alternating current source transistors, the structure combines the benefits of low supply voltage operation of conventional NMOS cross-coupled oscillators together with high current efficiency of the complementary push-pull oscillators. In addition, the 1/f noise upconversion is also reduced. The 40nm CMOS prototype exhibits an average FoM of 189.5 dBc/Hz over 4–5 GHz tuning range, dissipating 0.5mW from 0.5V power supply, while abiding by the technology manufacturing rules.
457Scopus© Citations 14 - Publication1-b Observation for Direct-Learning-Based Digital Predistortion of RF Power AmplifiersIn this paper, we propose a low-cost data acquisition approach for model extraction of digital predistortion (DPD) of RF power amplifiers. The proposed approach utilizes only 1-bit resolution analog-to-digital converters (ADCs) in the observation path to digitize the error signal between the input and output signals. The DPD coefficients are then estimated based on the direct learning architecture using the measured signs of the error signal. The proposed solution is proved to be feasible in theory and the experimental results show that the proposed algorithm achieves equivalent performance as that using the conventional method. Replacing high resolution ADCs with 1- bit comparators in the feedback path can dramatically reduce the power consumption and cost of the DPD system. The 1-bit solution also makes DPD become practically implementable in future broadband systems since it is relatively straightforward to achieve an ultra-high sampling speed in data conversion by using only simple comparators.
530Scopus© Citations 14 - PublicationA 1.8–2.3 GHz broadband Doherty power amplifier with a minimized impedance transformation ratioIn this paper, the design and measurement results of a 1.8 GHz to 2.3 GHz broadband Doherty power amplifier (DPA) are reported. A modified load modulation network is designed to minimize impedance transformation ratio over the entire dynamic range for the purpose of extending the operating bandwidth. Experimental results show that the drain efficiency of the proposed DPA maintains above 50% and 63% with continuous wave input signal powers of 26 dBm and 34 dBm, respectively, from 1.8 GHz to 2.3 GHz. When stimulated by a 60-MHz, 12- carrier UMTS signal at 2.14 GHz, the proposed DPA achieved an average efficiency of 53% at 7.6 dB back-off, while the corresponding adjacent channel leakage ratio is linearized to -48.4 dBc with digital predistortion.
335Scopus© Citations 4 - PublicationA 1/f noise up-conversion reduction technique for voltage-biased RF CMOS oscillatorsIn this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest impedance path. The asymmetric oscillation waveform results in an effective impulse sensitivity function of a nonzero dc value, which facilitates the 1/f noise upconversion into the oscillator's 1/f3 phase noise. We demonstrate that if the ω0 tank exhibits an auxiliary resonance at 2ω0, thereby forcing this current harmonic to flow into the equivalent resistance of the 2ω0 resonance, then the oscillation waveform would be symmetric and the flicker noise upconversion would be largely suppressed. The auxiliary resonance is realized at no extra silicon area in both inductor-and transformer-based tanks by exploiting different behaviors of inductors and transformers in differential-and common-mode excitations. These tanks are ultimately employed in designing modified class-D and class-F oscillators in 40 nm CMOS technology. They exhibit an average flicker noise corner of less than 100 kHz.
567Scopus© Citations 99 - PublicationA 1/f noise upconversion reduction technique applied to class-D and class-F oscillatorsThe 1/f (flicker) noise upconversion degrades the close-in spectrum of CMOS RF oscillators. The resulting 1/f3 phase noise (PN) can be an issue in PLLs with a loop bandwidth of <;1MHz, which practically implies all cellular phones. A previously published noise-filtering technique [1] and adding resistors in series with gm-device drains [2] have shown significant reduction of the 1/f3 oscillator PN corner. However, the former needs an additional tunable inductor and the latter degrades PN in the 20dB/dec region.
988Scopus© Citations 36 - Publication100% Converter-Interfaced generation using virtual synchronous generator control: A case study based on the irish systemThe increase in the use of Converter-Interfaced Generation (CIG) in the power system will require these generators to not only feed the power but also establish the voltage and maintain the grid stability. Virtual Synchronous Generator (VSG) control of the CIG is proposed to fulfill this requirement since it mimics the dynamics of synchronous generation. This paper takes the all-Island Irish transmission system as an example to investigate the frequency stability of the system as it migrates towards 100% CIG under VSG control and quantifies the minimum conditions for frequency support to sustain the system under 100% CIG. Simulations are carried out considering the worst contingency in the Irish grid which is the loss of largest infeed, namely, the disconnection of the HVDC interconnector to the UK. The results are compared and discussed considering other scenarios that include primary frequency control of conventional power plants.
69Scopus© Citations 20 - PublicationA 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS(IEEE, 2017-12-26)
; ; ; ; ; This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.594Scopus© Citations 12 - PublicationA 2.0–2.5 GHz frequency-selectable oscillator for digital predistortion model identification of RF power amplifiersThis paper presents the design of a frequency selectable oscillator used as part of a new data acquisition architecture for digital predistortion (DPD) of RF power amplifiers (PAs). The proposed architecture aims to alleviate the requirement of high sampling rate analog-to-digital-converters (ADCs) in the data acquisition loop. The oscillator utilizes switchable capacitors with a digital control scheme and is capable of operating between 2.0 GHz and 2.5 GHz with an approximate frequency step size of 512 kHz.
313Scopus© Citations 1 - PublicationA 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOSThis paper introduces a phase shifter based on switched filters for mm-wave 5G MIMO transmitters. It is realized in 22 nm FD-SOI CMOS and exploits the use of back-gate biasing. The new approach features strong tolerance to process, voltage and temperature (PVT) variations and thus can maintain low phase error with fine phase tuning capability supporting a large bandwidth. Measurement results show that the 4-bit phase shifter achieves 3.5° rms phase error at 28 GHz. The proposed phase shifter can maintain <5° of the worst-case rms phase error when operating across 24 to 29.5 GHz resulting in 20.56% fractional bandwidth which is the largest among the published switched-filter phase shifters to date.
81Scopus© Citations 1 - Publication28/38 GHz Dual-band Dual-polarized Highly Isolated Antenna for 5G Phased Array ApplicationsThis paper proposed a new dual-band dual-polarized array antenna operating at 28 GHz and 38 GHz for 5G communication applications. Three stacked patches are adopted to achieve the dual-band operation. The lower band from 27.48 to 28.50 GHz is achieved by using the lower large patch, which is couple-fed by the middle patch. While the upper band from 36.94 to 40.43 GHz is achieved by using the middle and upper patches. The two patches resonant at 38 and 40 GHz respectively and the two resonant modes coupled together, which greatly enhances the upper band. To increase the polarization isolation in the lower band, a shorting pin connecting the lower patch and ground is utilized. Taking advantages of the multi-layer technology, the position of the vertical feeding probe between the middle patch and lower patch is slightly shifted to ensure the good impedance matching in both lower band and upper band. For the antenna element, the simulated -12 dB bandwidths are 27.48-28.50 GHz and 36.94-40.43 GHz for the two bands, respectively. The in-band gains are over 6 dBi in the lower band, and over 4 dBi in the upper band. For the 2×2 antenna array, the isolations are better than 20 dB in both bands.
1334Scopus© Citations 10 - Publication2D Non-separable Linear Canonical Transform (2D-NS-LCT) based cryptography(2017-04-27)
; ; ; ; ; The 2D non-separable linear canonical transform (2D-NS-LCT) can describe a variety of paraxial optical systems. Digital algorithms to numerically evaluate the 2D-NS-LCTs are not only important in modeling the light field propagations but also of interest in various signal processing based applications, for instance optical encryption. Therefore, in this paper, for the first time, a 2D-NS-LCT based optical Double-random-Phase-Encryption (DRPE) system is proposed which offers encrypting information in multiple degrees of freedom. Compared with the traditional systems, i.e. (i) Fourier transform (FT); (ii) Fresnel transform (FST); (iii) Fractional Fourier transform (FRT); and (iv) Linear Canonical transform (LCT), based DRPE systems, the proposed system is more secure and robust as it encrypts the data with more degrees of freedom with an augmented key-space.416 - Publication3 Dimensional analysis of holographic photopolymers based memories(Optical Society of America, 2005-05-02)
; ; ; ; ; ; ; One of the most interesting applications of photopolymers is as holographic recording materials for holographic memories. One of the basic requirements for this application is that the recording material thickness must be 500 µm or thicker. In recent years many 2-dimensional models have been proposed for the analysis of photopolymers. Good agreement between theoretical simulations and experimental results has been obtained for layers thinner than 200 µm. The attenuation of the light inside the material by Beer’s law results in an attenuation of the index profile inside the material and in some cases the effective optical thickness of the material is lower than the physical thickness. This is an important and fundamental limitation in achieving high capacity holographic memories using photopolymers and cannot be analyzed using 2-D diffusion models. In this paper a model is proposed to describe the behavior of the photopolymers in 3-D. This model is applied to simulate the formation of profiles in depth for different photopolymer viscosities and different intensity attenuations inside the material.340Scopus© Citations 50 - PublicationA 30-GHz Class-F23 Oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz l/f3 CornerThis paper presents a mmW frequency generation stage aimed at minimizing phase noise via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A second-harmonic tank resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for shortest and well controlled common-mode current return path. Class-F operation with third-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10 GHz tank at the 30 GHz frequency generation while providing implicit divide-by-3 functionality. The proposed 27.3-31.2 GHz oscillator is implemented in 28-nm CMOS. It achieves phase noise of-106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dB at 27.3GHz. Its flicker phase-noise (1/f3) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.
316Scopus© Citations 10 - PublicationA 34-year simulation of wind generation potential for Ireland and the impact of large-scale atmospheric pressure patterns(Elsevier, 2017-06)
; ; ; ; To study climate-related aspects of power system operation with large volumes of wind generation, data with sufficiently wide temporal and spatial scope are required. The relative youth of the wind industry means that long-term data from real systems are not available. Here, a detailed aggregated wind power generation model is developed for the Republic of Ireland using MERRA reanalysis wind speed data and verified against measured wind production data for the period 2001–2014. The model is most successful in representing aggregate power output in the middle years of this period, after the total installed capacity had reached around 500 MW. Variability on scales of greater than 6 h is captured well by the model; one additional higher resolution wind dataset was found to improve the representation of higher frequency variability. Finally, the model is used to hindcast hypothetical aggregate wind production over the 34-year period 1980–2013, based on existing installed wind capacity. A relationship is found between several of the production characteristics, including capacity factor, ramping and persistence, and two large-scale atmospheric patterns – the North Atlantic Oscillation and the East Atlantic Pattern.362Scopus© Citations 23 - PublicationA 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOSA mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.
745Scopus© Citations 143 - PublicationA 60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoMA 60 GHz frequency generator with implicit ÷3 divider is proposed in this work to improve the system-level efficiency and phase noise. A third-harmonic boosting technique is utilized to simultaneously generate 20GHz and sufficiently strong 60 GHz signals in order to avoid any divider operating at 60 GHz. The prototype is fabricated in 40nm CMOS and exhibits a phase noise of −100 dBc/Hz at 1MHz offset from 60 GHz carrier and 25% tuning range. The phase noise and FoMT (figure-of-merit with tuning range) are improved by 5 dB and 4.6 dB, respectively, compared to state-of-the-art.
479Scopus© Citations 11 - PublicationA 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit MultiplierThis paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed back for phase detection in a phase-locked loop. Third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator. A prototype of the proposed frequency generator is implemented in digital 40 nm CMOS. It exhibits a PN of -100 dBc/Hz at 1 MHz offset from 57.8 GHz and provides 25% frequency tuning range (TR). The achieved figure-of-merit (FoM) is between 179 and 182 dBc/Hz.
453Scopus© Citations 89 - PublicationAccelerated Projected Gradient Method for the Optimization of Cell-Free Massive MIMO DownlinkWe consider the downlink of a cell-free massive multiple-input multiple-output (MIMO) system where large number of access points (APs) simultaneously serve a group of users. Two fundamental problems are of interest, namely (i) to maximize the total spectral efficiency (SE), and (ii) to maximize the minimum SE of all users. As the considered problems are non-convex, existing solutions rely on successive convex approximation to find a sub-optimal solution. The known methods use off-the-shelf convex solvers, which basically implement an interior-point algorithm, to solve the derived convex problems. The main issue of such methods is that their complexity does not scale favorably with the problem size, limiting previous studies to cell-free massive MIMO of moderate scales. Thus the potential of cell-free massive MIMO has not been fully understood. To address this issue, we propose an accelerated projected gradient method to solve the considered problems. Particularly, the proposed solution is found in closed-form expressions and only requires the first order information of the objective, rather than the Hessian matrix as in known solutions, and thus is much more memory efficient. Numerical results demonstrate that our proposed solution achieves far less run-time, compared to other second-order methods.
178Scopus© Citations 5 - PublicationAccommodating Variability in Generation Planning(Institute of Electrical and Electronics Engineers, 2013-02)
; ; Many of the most commonly used generation planning models have been formulated in a way that neglects the chronological sequence of demand and the mixed-integer nature of generating units. The generator schedules assumed by these models are inaccurate and become increasingly divorced from real schedules with increasing variability. This paper seeks to characterize and quantify the limitations of these models over a broad set of input parameters. For an illustrative set of test systems, wind capacities and generator types, annual system costs are determined for all combinations of generating units using a unit-commitment model, which captures the chronological behavior of units and a dispatch model which does not. It is seen that the relative performance of the dispatch model is highly system specific but generally degrades with increasing variability. The difference in cost estimates between the models is decomposed into start costs, starts avoidance and average cost estimation error. The impact on least-cost portfolios is shown and finally sensitivities are performed with the addition of hydro and nuclear power to assess their impact.1554Scopus© Citations 70