Electrical and Electronic Engineering Theses

Permanent URI for this collection

http://hdl.handle.net/10197/6690

This collection is made up of doctoral and master theses by research, which have been received in accordance with university regulations.

For more information, please visit the UCD Library Theses Information guide.

Browse

Browsing Electrical and Electronic Engineering Theses by Title

Now showing 1 - 20 of 37
  • Publication
    Advanced distribution network modelling with distributed energy resources
    (University College Dublin. School of Electrical and Electronic Engineering  , 2015)
    O'Connell, Alison 
    The addition of new distributed energy resources, such as electric vehicles, photovoltaics, and storage, to low voltage distribution networks means that these networks will undergo major changes in the future. Traditionally, distribution systems would have been a passive part of the wider power system, delivering electricity to the customer and not needing much control or management. However, the introduction of these new technologies may cause unforeseen issues for distribution networks, due to the fact that they were not considered when the networks were originally designed.This thesis examines different types of technologies that may begin to emerge on distribution systems, as well as the resulting challenges that they may impose. Three-phase models of distribution networks are developed and subsequently utilised as test cases. Various management strategies are devised for the purposes of controlling distributed resources from a distribution network perspective. The aim of the management strategies is to mitigate those issues that distributed resources may cause, while also keeping customers' preferences in mind.A rolling optimisation formulation is proposed as an operational tool which can manage distributed resources, while also accounting for the uncertainties that these resources may present. Network sensitivities for a particular feeder are extracted from a three-phase load flow methodology and incorporated into an optimisation. Electric vehicles are the focus of the work, although the method could be applied to other types of resources. The aim is to minimise the cost of electric vehicle charging over a 24-hour time horizon by controlling the charge rates and timings of the vehicles. The results demonstrate the advantage that controlled EV charging can have over an uncontrolled case, as well as the benefits provided by the rolling formulation and updated inputs in terms of cost and energy delivered to customers.Building upon the rolling optimisation, a three-phase optimal power flow method is developed. The formulation has the capability to provide optimal solutions for distribution system control variables, for a chosen objective function, subject to required constraints. It can, therefore, be utilised for numerous technologies and applications. The three-phase optimal power flow is employed to manage various distributed resources, such as photovoltaics and storage, as well as distribution equipment, including tap changers and switches. The flexibility of the methodology allows it to be applied in both an operational and a planning capacity.The three-phase optimal power flow is employed in an operational planning capacity to determine volt-var curves for distributed photovoltaic inverters. The formulation finds optimal reactive power settings for a number of load and solar scenarios and uses these reactive power points to create volt-var curves. Volt-var curves are determined for 10 PV systems on a test feeder. A universal curve is also determined which is applicable to all inverters. The curves are validated by testing them in a power flow setting over a 24-hour test period. The curves are shown to provide advantages to the feeder in terms of reduction of voltage deviations and unbalance, with the individual curves proving to be more effective. It is also shown that adding a new PV system to the feeder only requires analysis for that system.In order to represent the uncertainties that inherently occur on distribution systems, an information gap decision theory method is also proposed and integrated into the three-phase optimal power flow formulation. This allows for robust network decisions to be made using only an initial prediction for what the uncertain parameter will be. The work determines tap and switch settings for a test network with demand being treated as uncertain. The aim is to keep losses below a predefined acceptable value. The results provide the decision maker with the maximum possible variation in demand for a given acceptable variation in the losses. A validation is performed with the resulting tap and switch settings being implemented, and shows that the control decisions provided by the formulation keep losses below the acceptable value while adhering to the limits imposed by the network.
      422
  • Publication
    BJT Based Precision Voltage Reference in FinFET Technology
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Kamath, Umanath Ramachandra 
    FinFET technology has been widely adopted for high-performance computing chips and large mixed-signal System-on-Chip (SoC). This work addresses the problem of realizing high-precision voltage references in deep nanoscale FinFET process technology. Such a problem requires consideration both at the device and circuit levels as well as their co-optimization. Hence, this thesis begins with a BJT device and its characterization in 7-nm FinFET process followed subsequently by utilizing these constructed device models for circuit realization. This work highlights the BJT device SPICE modeling and characterization results in 7-nm FinFET CMOS technology, giving special emphasis to the BJT’s variability and process spread in order to provide insights into key device-circuit interactions. This guides the optimization choices for the designer, which is crucial for analog design in deep nanoscale CMOS. BJT device characterization in 7-nm FinFET process is essential to enable not only precision voltage references, but also for other circuits such as temperature sensors, current references which use BJT at its core. Besides, the key parameters characterized helps predict the limit of achievable precision due to the underlying device inaccuracy. Subsequently, this achieves the aim of quantifying the system application performance. Measurement results of two test-chip device arrays are presented to demonstrate the feasibility of using BJTs in FinFET CMOS and the associated operating conditions (bias current density) optimal for achieving high-precision circuits. Instead of using the standard BJT layout structure available from the foundry, a merged layout structure was implemented which further saves 20% of the silicon area. This area saving layout of the BJT device could be useful for certain applications such as distributed reference or thermal sensors in large SoC. In the next part of the work, we present a 1-V precision voltage reference with a programmable temperature coefficient (‘temp-co’).The voltage reference is based on a parasitic BJT realized within the process steps available in the chosen 7-nm FinFET technology and characterized in the earlier part of this thesis. The targeted precision for this work was achieved by employing trimming techniques to manage the process spread and using two curvature compensation methods. The architecture together with these techniques ensured that the circuit was capable of handling any variation in the device models since the process technology was not mature at the time of design. In addition, the proposed architecture also is capable to program the ‘temp-co’ which is shown to be beneficial in certain applications, to compensate for any system-level thermal degradation. The reference circuit was implemented in a 7-nm TSMC FinFET technology and achieves a maximum inaccuracy of±0.2% and a minimum temp-co of 6ppm/°C from -45°C to 125°C,which is favourable in comparison to state-of-the-art voltage references. Furthermore, its temp-co is digitally programmable between -7 mV/100°C to +8 mV/100°C using a 7-bit flat-trim control code, which is an additional feature of architecture to cope with thermal gradients across large SoC by compensating system-level performance across temperature. The proposed voltage reference has a line regulation of 0.1%/V, and occupies area of 0.078 mm2.
      64
  • Publication
    BLE Transceiver/4G Mobile PLL for Wireless Applications
    (2019-01)
    Kuo, Feng-Wei 
    The Internet of Things (IoT) and cellular (mobile) systems are the most promising technologies of the next Fifth Generation (5G) of the mobile broadband network. The radio technological revolution for wireless communications has already begun. In the past, IoT wireless communications have been used in many industries, and a variety of new applications have been developed. As a result, the next-generation wireless technology, popularly known as 5G, promises to deliver new levels of capability and efficiency by supporting a diverse range of future applications, which can change the way we live, work, and communicate with each other. Based on the future 5G applications, this thesis is composed of 5 parts. The first objective of this thesis is to introduce the demands placed on monolithic local oscillators (LO), realized as RF phase-locked loops (PLLs), which are particularly exacting, especially with regard to their integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLL has become a challenging task. For instance, narrow bandwidth systems, such as the GSM of 2G and the enhanced data rate for the WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand particularly low in-band (IB) PN in a mobile cellular system. However, there has arisen a new class of operation for RF oscillators and 2-way parallelism of TDC with PVT stabilization to fill the performance/power gap in the ultra-high figure of merit (FoM) and ultra-low phase noise space. The proposed oscillator and TDC should also be implemented as the heart of a PLL system to demonstrate their superiority in a real implementation. The second objective of this thesis is to introduce an all-digital PLL that employs a digitally controlled oscillator (DCO) with switching current sources to reduce the supply voltage and power without sacrificing its phase noise and start-up margins. The DCO also reduces its 1/f noise, allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during direct DCO data modulation. The switching power amplifier (PA) integrates its matching network while operating in class E/F2 to maximally enhance its efficiency. The transmitter is realized in 28-nm CMOS and satisfies all metal density and other manufacturing rules. Another system-level approach is to develop the first ever fully discrete-time superheterodyne receiver for IoT applications, such as Bluetooth low-energy (BLE). It exploits the fast switching speed and low internal capacitances of deep-nanoscale CMOS devices to realize a high intermediate-frequency (IF) architecture based on switchedcapacitor- based charge-domain bandpass filtering. The power consumption is minimized by aggressively reducing the size of the MOS devices and judiciously applying a sampling-rate decimation. The resultant increase in flicker noise is mitigated by placing the IF frequency beyond the flicker corner frequency. Likewise, the decimation-induced aliasing is mitigated by DT filtering of preceding stages. To improve the power efficiency of a Bluetooth low energy transceiver by exploiting a novel digitally controlled oscillator, a class E/F2 switched-mode PA and a new discrete-time (DT) receiver (RX) are adapted to achieve high out-of-band linearity, low noise and low power consumption. In addition, an integrated on-chip matching network serves both the PA and LNTA, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The third objective of this thesis is to introduce an ultra-low voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5V supply. While its DCO runs directly at 0.5 V, an internal switched-capacitor DC–DC converter ‘doubles’ the supply voltage to all the digital circuitry and particularly regulates the TDC supply to stabilize its resolution, thus maintaining fixed in-band phase noise across process, voltage and temperature (PVT) variation. Moreover, the impact of voltage supply scaling on the power consumption and performance of a discrete-time (DT) superheterodyne receiver (RX) for IoT applications and realized in deep nanoscale CMOS using inverter-based gm and switched capacitors has been studied. The power supply is partitioned into three separate domains: RF, IF processing, and clocking, which allows them to be independently regulated to assess their respective impacts. The DT-RX maintains its functionality, albeit with some acceptable loss of performance, when the core supplies are varied by as much as an octave, i.e. from the nominal 1.1V down to 0.55 V. The DT-RX IC is then connected to a switched-capacitor based voltage doubler array on a companion IC die such that the DT-RX can be powered at the octave range of 0.275–0.55V from an energy harvester. The sensitivity at the doubler’s 0.275/0.55V input is -85/-95dBm while consuming 1.0/2.4mW. The fourth objective of this thesis is to introduce a sub-GHz transmitter (TX) with a physically merged DCO and digital power amplifier (DPA). The matching transformer of single-ended DPA is placed inside the DCO transformer to save c. 50% of area. The resulting DCO pulling is compensated via a feedback path and an inter-winding cancellation capacitor suppresses the 2nd harmonic. Fabricated in 16-nm FinFET CMOS, the DPA reaches 51% efficiency at 11dBm output with <-55 dBc second harmonic (HD2). The fifth objective of this thesis is to improve the power efficiency and frequency range of a dual-frequency-band radar system by exploiting a third-harmonic boosting DCO simultaneously generating 22.5–28GHz and sufficiently strong 68–84 GHz signals to satisfy short-range radar and medium/long range radar requirements.
      2614
  • Publication
    Broadband High Efficiency Power Amplifiersfor RF Front-Ends of Wireless Transmitters
    (University College Dublin. School of Electrical and Electronic Engineering, 2022)
    Chu, Chenhao 
    ;
    0000-0002-2562-9599
    This thesis explores Power Amplifier (PA) architectures for Radio Frequency (RF) front-ends of transmitters in Fifth Generation (5G) wireless communication systems. New PA operation classes and new efficiency enhanced architectures are presented with comprehensive analyses, well-designed state-of-art prototypes, and excellent experimental results. Firstly, a new class of PA, designated as Class-iF-1, is proposed, which utilizes input harmonics to achieve high efficiency with enhanced linearity performance beyond the conventional Class-F-1 PA. The Amplitude-to-Amplitude (AM/AM) profile of the conventional Class-F-1 PA is mathematically modeled as a function of input drive level. Theoretical derivation shows that the appropriate utilization of input nonlinearity poses a solution to rectify the double inflection characteristics of conventional Class-F-1 PA, which consequently, can be realized by proper manipulation of second harmonic source impedance. A broadened second harmonic design space over the open-circuit region is proposed. Secondly, a new solution for phase compensation in the Sequential Load Modulated Balanced Amplifier (SLMBA) architecture is presented. By using proper harmonic tuning in the control amplifier carrier branch, the load trajectory of the balanced amplifier can be made close to the real axis, which is beneficial to recovering peak output power and efficiency at both Output Power Back-Off (OPBO) and saturation of the SLMBA in wideband operation. Thirdly, a novel Waveform Engineered Sequential Load Modulated Balanced Amplifier (W-SLMBA) is proposed, which uses a continuous Class-F-1 Control Amplifier (CA) to manipulate the impedance trajectory of the Balanced Amplifier (BA). It is demonstrated that the use of the continuous Class-F-1 CA can trigger a unique impedance load modulation mechanism by which the fundamental impedance of the BA is shaped by the varying second harmonic load reactance of the CA. Theoretical derivations reveal that this special load modulation yields extended design space for the SLMBA, wherein high efficiency can be achieved over a wide bandwidth and OPBO. Fourthly, the design methodology of a broadband RF-input SLMBA is introduced, with extended high efficiency design space, by introducing the second harmonic load manipulation over an enlarged range for the CA. The extension of CA load design space not only can provide the time-domain varying drain current waveform inside the entire design continuum, but also allows maintaining high efficiency OPBO over an extended operation bandwidth. Last but not least, the impact of input nonlinearity in SLMBA architecture is investigated. The Class-F-1 operation is selected as the solution for CA branch due to its advantage of high OPBO performance, efficiency flatness and immunity versus second harmonic source phase ¿G2S, which leads to the adoption of Class-B/J operation for BA. While Class-F-1 CA is immune to the second harmonic source variation, the safe design space for BA lands in the region where ¿G2S is over (-90¿, 90¿).
      6
  • Publication
    Broadband radio frequency power amplifiers for 5G wireless communications
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Xu, Y. (Yang) 
    ;
    0000-0001-6252-6997
    Power amplifier (PA) is one of the key components in radio frequency (RF) front-end transceiver and its performance has a critical impact on wireless systems. In the coming fifth-generation (5G) wireless telecommunication system, due to the growing data traffic, there are increasing demands for higher data rate, wider bandwidth and higher spectrum efficiency. Moreover, modulated signals with high peak-to-average power ratio (PAPR) are widely adopted in 5G systems, requiring PAs to provide high power dynamic range. In this thesis, PA design methodologies aiming at performance enhancement with respect to bandwidth, efficiency, linearity and power dynamic range are comprehensively discussed under 5G sub-6 GHz applications. In each topic, both theoretical analysis and circuit verification are provided. Firstly, the broadband solution for maintaining PA's high efficiency is discussed. The broadband continuous mode operation is analyzed. Based on it, a practical design methodology to construct output matching networks for broadband continuous mode PA is proposed. This solution is designed for Monolithic Microwave Integrated Circuit (MMIC) process which enables compact circuit design with high power density. A prototype PA with 0.25 um Gallium Nitride (GaN) MMIC process is implemented. Secondly, in addition to broadband continuous mode PA design, its linearity performance is analyzed. The simulation reveals that the linearity behaviour varies with frequency inside the extended impedance space provided by continuous mode. To unify the linearity in broadband, a circuit level linearity compensation method adopting clipping contours is presented. A design example implemented with 0.25 um GaN HEMT is demonstrated to validate the method. Thirdly, the bandwidth and efficiency performance at output power back-off is investigated. A design methodology for the broadband Doherty power amplifier (DPA) is presented. To extend the bandwidth and output power back-off range simultaneously, a modified load modulation network is proposed. Based on the analysis and case studies, a series of generalized formulas for estimating design parameters are then introduced, offering broadband solution for arbitrary current ratio and power back-off. A prototype DPA is demonstrated and implemented with packaged GaN devices using proposed formulas. The last part proposes another design methodology for enhancing efficiency at output power back-off. A new way of load modulation is realized with a three-stage load modulated power amplifier architecture. This new load modulation mechanism enables flexible output power back-off and efficiency enhancement within large power dynamic range. Under the proposed architecture, the power back-off can be reconfigured without redesigning the circuit.
      26
  • Publication
    Channel Estimation and Receiver Design for FBMC-OQAM and OTFS Modulation Schemes
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Singh, Vibhutesh Kumar 
    Future generation wireless communication standards aim to have notable improvements upon the current communication standards. For example, the visions of 5th Generation (5G) and beyond communication systems include peak data transfer rate of 20 Gb/s, massive communication device capacity per unit area ( 10^6 per square km), end to end latency less than 1 ms, reliability and flexibility for supporting various applications when compared to the current systems. These critical visions should also be achieved in several complicated communication scenarios, including indoor, urban, dense urban, rural, and high-velocity scenarios. Many current systems utilize a multicarrier modulation technique called cyclic prefixed orthogonal frequency division multiplexing (CP-OFDM). Although having multiple advantages, e.g., simple channel estimation and low-complexity channel equalization, the drawbacks of CP-OFDM, e.g., reduced spectral efficiency, problem of high out-of-band emissions, and degraded bit error rate (BER) performance in high-velocity communication scenarios makes it difficult for CP-OFDM to achieve future visions. As a result, several waveforms such as filterbank multicarrier with offset quadrature amplitude modulation (FBMC-OQAM) and orthogonal time frequency space (OTFS) are suggested in the literature to overcome CP-OFDM’s drawbacks. This thesis examines these OFDM alternative schemes with a particular focus on channel estimation, which in theory is not as straightforward as in OFDM. The notable contributions made to the literature through this thesis are: • An in-depth analysis of the FBMC-OQAM system’s intrinsic interference and its symmetry properties. • Proposal of a Generalized Least Squares based channel estimation technique which takes into account the correlated nature of noise-plus-interference of the FBMC-OQAM system. • Theoretical analysis of channel estimation mean squared error (CE-MSE) for conventional virtual symbol and Generalized Least Squares based channel estimation scheme. • Analysis of the OTFS received symbol’s variance, and proposal of a minimum mean squared error (MMSE) channel, estimator. • A low-complexity maximum likelihood (ML) channel path detector for the OTFS system is proposed. The proposed channel estimation (CE) schemes for FBMC-OQAM and OTFS systems are shown to outperform significantly compared to state of the art. The proposed schemes’ performance gains are demonstrated through theoretical CE-MSE analysis, bit error rate (BER), and CE-MSE simulations.
      191
  • Publication
    A Circuit Design Journey from Room Temperature to Cryo Temperature
    (University College Dublin. School of Electrical and Electronic Engineering, 2020)
    Esmailiyan, Ali 
    The continual advancement of CMOS technology results in faster and more power efficient digital processing. Concurrently, the supply voltage of CMOS circuits is scaled lower and this leads to smaller voltage headroom, which raises challenges in designing analog circuits with every new CMOS technology node. To overcome these challenges, there have been significant interests in time-based analog-todigital converters (ADCs). To convert an input voltage signal to time domain, some kind of voltage-to-time conversion (VTC) is needed. The linearity of this VTC usually limits the performance of time-based ADCs. To solve these problems, this thesis proposes and realizes in TSMC 28-nm CMOS two new techniques in the time-based ADCs using a VTC. In the first design, the proposed ultra-low-voltage ADC makes use of a Dickson charge pump circuit (Dickson CP) as part of VTC to convert the input analog voltage into time domain by modulating the slope of the ramp. In the second design, to compensate the nonlinearity in the generated ramp signal from the Dickson CP, a digital compensation scheme is proposed. As the Moore’s law of scaling of transistors is losing its momentum, there have been significant interests aiming to extend the exponential growth in computing power by means of “quantum computing", which promises to solve sophisticated and currently intractable problems in various applications, such as simulation of chemical reactions, modeling financial transactions, finding cure for COVID-19, etc. In order to control the extremely fragile quantum bits (qubits) with an accurate manipulation and readout, the quantum computers also require extremely low (cryogenic) temperatures to operate so as to preserve their coherent superposition state. The second part of this thesis presents an interface circuitry which is located on the same die and close to the quantum experiment cell. This includes key building blocks, such as digital-to-analog converters (DAC) and detectors. The proposed circuits are designed to operate at cryogenic temperatures around 4 K. They are implemented in 22-nm FDSOI CMOS from GlobalFoundries. Cryogenic test setup and off-chip controlling circuits are also presented.
      115
  • Publication
    Circularly Polarized Antennas for 5G Millimetre-Wave Communications
    (University College Dublin. School of Electrical and Electronic Engineering, 2022)
    Sadeghi-Marasht, Samaneh 
    The need of a higher data rate, lower latency, and cost efficiency led to the fifth-generation (5G) emerging as a new communication standard. This generation includes many unused frequencies with high available bandwidth channels that can provide higher capacities such as millimeter-wave (mm-wave) bands. One of the main challenges of working at high frequencies of this generation is path loss that needs to be addressed. To overcome this issue, a high gain antenna with a small size is required. Consequently, the first major question arises: how to effectively increase the gain and efficiency of the antenna at a high frequency with a small size. Importantly, it is vital to transport as much as data is possible without any sensitivity to the alignment of the transmitter or receiver antenna that can be satisfied by using circularly polarized (CP) radiating waves. Thus, the second research question emerges: how to provide high gain small size antenna with CP at high frequencies. To address the first two major research questions in this thesis we designed a miniature dual-band CP antenna that works at 28 GHz and 38 GHz with high gain. This antenna can be implemented in mobile devices, unmanned aerial vehicles (UAVs), and base stations (BSs) because of the small sizes of 11 × 14 × 0.508 mm3. For getting a deep insight into the structure and the design procedures of the dual-band antenna, characteristic mode analysis (CMA) is employed. Note that the CMA is not sensitive to the feeding position and the material in this analysis is not lossy. Therefore, after using CMA, the optimization is conducted in the full-wave simulation as the feeding is added to the structure, and the material is lossy. The single CP antenna covered the bands of 27-28.4 GHz and 34.7-40 GHz, with a maximum gain of 6.3 dBiC and 5.51 dBiC at 28 GHz and 38 GHz, respectively, whereas the radiation efficiency is 94% and 96% with the ARBW of 2.5% and 1.5%. A phased antenna array is then constructed to provide a higher gain for this designed dual-band antenna. In a phased antenna array we consider four designed single element antennas close to each other to create a 2 × 2 antenna array with high gain at 28 GHz and 38 GHz. For a 4 × 4 antenna array, an electromagnetic band-gap (EBG) is used to reduce the mutual coupling between elements in the array. The radiating signals will be sent to different users with circular polarization via electronic beamforming. The position of each antenna element is also optimized to provide the constructive radiating wave towards our desired directions. The array was able to steer the beam between -26.5 to 29.5 degrees for the lower band and -29.5 to 35.5 degrees for the higher band with the maximum gain of 12.8 dBiC and 11.5 dBiC, respectively. Another method to enhance the gain is implementing a lens structure in front of the radiating antenna. Here, a significant challenge is to maintain the CP of the incoming CP wave while the gain is increased. Therefore, the third research question is how to design a lens with the capability of enhancing the gain and keeping the CP when the lens is fed by a CP antenna source. Concerning the third major research question, in this thesis, we designed a CP lens structure. First, a multi-layer lens with a thickness of 2.03 mm was designed, and then a one-layer lens structure with a thickness of just 0.508 mm was made. The lens was located in front of different radiating antennas. These lens structures resulted in significant gain enhancement for various feeding antennas working at 28 GHz. The unit cell of the one-layer lens can provide a broad phase shift compared to the multi-layer counterpart. The proposed lens structures not only increased the gain of the incoming CP wave but also kept its polarization to overcome the issues of reflectivity, absorption, inclement weather, and mis
      16
  • Publication
    Collaborative and Context-Aware Applications for Intelligent and Green Transportation
    (2018-12-06)
    Gu, Yingqi 
    In this thesis, we present several context-aware and collaborative applications of electric and plug-in hybrid vehicles in the context of intelligent transportation systems, with a main focus on the design of control and optimisation algorithms to maximise the performance of such vehicles in different practical scenarios. This gives rise to four topics to be discussed in the thesis. The first topic focuses on the design of speed advisory systems for different road users. In Chapter 3, we present a framework for minimising the energy consumptions for a group of electric vehicles in a distributed manner. Using this framework, we extend the ideas of this design to the case of cyclists, where now we maximise the overall health benefits for a group of cyclists sharing a common route. In both cases, we apply a recently derived consensus mathematical result for solving both convex and quasi-convex optimisation problems with consensus constraints. The efficacy of our proposed algorithm is verified through many simulation studies. The second topic is concerned with a new design of the energy management system for plug-in hybrid electric vehicles (PHEVs) by taking into account the availability of the upcoming renewable energy generation. In Chapter 4, we introduce distributed algorithms for PHEVs to switch on/off their electric motors such that some utility functions can be maximised while achieving a demand and supply balance for power grids when vehicles travel back for recharging. This idea is then extended for the case of plug-in hybrid electric buses (PHEBs) in Chapter 5, focusing on maximising the environmental benefits of buses with some energy constraints to be satisfied. The third topic introduces a novel context-aware engine management system for PHEVs to optimally orchestrate switching between different operational modes so that the environmental benefits on pedestrians can be reached to a maximum. In Chapter 6, we present details of our design for such a system taking account of many factors in practice. We implement the proposed system in a hardware-in-the-loop platform, embedded with a real PHEV, to illustrate the efficacy of our proposed approach. The last topic investigates the ability of simple macroscopic information to identify changes in nominal urban traffic flows. In Chapter 7, we focus on using junction turning probabilities to infer the occurrence of anomalies in traffic patterns. Finally, several simulation studies are conducted in a popular mobility simulator to demonstrate the capabilities of our proposed method.
      917
  • Publication
    Contributions to the theory and development of low-jitter bang-bang integrated frequency synthesizers
    (University College Dublin. School of Electrical and Electronic Engineering, 2022)
    Avallone, Luca 
    The advent of next-generation wireless standards demands ever-increasing data-rate communication systems. It mainly involves a higher carrier frequency to take advantage of wider bandwidth channels and more complex modulation schemes to pack more information into each symbol. In this context, the bottleneck is represented by the frequency synthesizer used to generate the local oscillator signal for the transceiver, which has to operate under stringent low output jitter requirements. Such performance must be provided at low power dissipation and area consumption in order to meet the requirements of low-cost and high integration level of the modern communication systems. The digital phase locked loop architecture can meet the required jitter performance while synthesizing fractional-N frequencies. Such PLLs offer significant advantages over their traditional analog counterpart in terms of area occupation, flexibility and scalability in advanced deep sub-µm CMOS technologies. The digital PLL topology based on a bang-bang phase detector, denoted bang-bang PLL, which is a single bit digital phase detector, leads to a less complex and more power-efficient architecture, but, on the other hand, it also introduces a hard nonlinearity in the loop, making the analysis of the bang-bang topology more challenging than in the multi-bit case. A comprehensive phase noise analysis of bang-bang digital PLLs is presented which overcomes the limitations of previous models and it is valid in all cases where physical noise sources (i.e. reference and DCO) are dominant with respect to quantization errors. In particular, (i) input-referred jitter is estimated by means of a linear time-domain analysis derived from a nonlinear DPLL model, and (ii) phase noise spectra are predicted using a discrete-time domain model that accounts for time-variant effects that arise from the intrinsic multirate nature of the DPLL. The possibility of accurately determining the DPLL jitter and phase noise spectra, enabled by the novel analysis presented in this thesis, is key to significantly speeding up the design-space exploration phase, since it allows one to perform quick and precise parametric sweeps. However, even when designed properly, bang-bang PLLs are affected by the unavoidable bang-bang phase detector quantization noise, which is added on top of the intrinsic reference and DCO phase noise. The quantization noise can be appreciated in the PLL's output spectrum as increased in band noise with respect to the analog counterpart, that, in fact, still achieves superior performance in terms of jitter-power. This results in worse integrated jitter performance for the same intrinsic levels of reference and oscillator phase noise. To overcome the binary phase detector quantization noise in DPLLs, state-of-the-art works rely on a multi-bit time-to-digital converter to digitize the PLL phase error with a physical resolution below the input jitter, leading to increased design complexity, with an associated area and power penalty. In order to overcome the ultimate limit of the bang-bang PLL, a digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping has been fabricated in a 28nm CMOS process. The prototype occupies a core area of 0.21 mm2 and draws 10.8 mW power from a 0.9 V supply. The integrated jitter is 69.52 fs and 80.72 fs for the integer-N and the fractional-N case, respectively. Achieving a jitter-power figure-of-merit of -251.5 dB in fractional-N mode, the proposed system effectively bridges the gap to analog implementations. The first chapter of this work is introductory, and is intended to give some background information needed to underpin the remaining part of the thesis. The following chapters, 2, 3 and 4, collect the results achieved during the PhD activity, and each of them is associated with a publication. In the last chapter, conclusions are drawn and the open points are discussed in order to be considered for future work.
      54
  • Publication
    Design considerations for a high power, medium frequency transformer for a DC-DC converter stage of a solid state transformer
    (University College Dublin. School of Electrical and Electronic Engineering  , 2016)
    Mumuluh, Roland Nshieteh 
    ii. ABSTRACTIn recent years, the solid state transformer concept has challenged the conventional low frequency transformer. The conventional transformer cannot store energy and its output is easily distorted as a result of perturbations at its input. In same manner, disturbances from the output unit such as harmonics along with reactive power, as well as load transients are reflected back to the input of the conventional transformer. The size of the low frequency transformer is significantly larger. The Solid state transformer challenges the traditional low frequency transformer in that it eradicates the aforementioned drawbacks and provides multifunctional features.In this thesis a reliable model to design and optimize a high power medium frequency transformer for a dc-dc converter that forms part of a solid state transformer is researched and established. The aim is to use this model to investigate how high can be the operating frequency for a medium frequency transformer to achieve maximum efficiency and minimum volume. The dc-dc converter consists of a transformer that provides isolation between a medium-voltage circuit and a low-voltage circuit in a distribution system, and power semiconductor devices. Transformer operation at medium frequency reduces size and volume due to the inverse relationship of transformer area product and frequency. However, at medium frequency, the transformer is less efficient as a result of increased losses due to skin and proximity effects and the temperature rise constraint. Unlike low power magnetic cores where there are standard sizes and dimensions, high power magnetic cores for medium frequency maybe designed depending on demand or in certain cases, using limited dimensional references. Thus, an optimised transformer design for high power medium frequency relies on how its dimensions are defined. The characteristics expected of a core material for high power medium frequency are that it should have a high saturation flux density; low core loss and the material should continuously operate at high temperatures. The findings revealed that the frequency can be as high as 10 kHz to achieve maximum efficiency and minimum volume. An optimum design depends upon the flux density, the winding current density, the numbers of primary turns, the operating frequency and the power level of the transformer. There is no point operating above 20 kHz as there is very little reduction in volume and the winding loss results to increased temperature and reduces the efficiency of the transformer.
      1329
  • Publication
    Design of an Immersive Human-Centric Cyber-Physical System for Additive Manufacturing
    (University College Dublin. School of Electrical and Electronic Engineering, 2022)
    Malik, Ammar 
    ;
    0000-0003-3473-0039
    Despite tremendous promises, Additive Manufacturing (AM) still faces many challenges to matching the standards of conventional manufacturing and reaching its full potential in bridging the gap between the consumer, the designer, and the production. Driven by these challenges, the research and industry communities are focused on not only making 3D printing machines work better either by designing robust control strategies or by designing advanced monitoring methodologies, but also on developing new ways to enable enhanced human interactions in a feedback loop. In this thesis, we design an immersive human-centric cyber-physical system, named I-nteract, to provide a framework to develop intuitive and user-friendly interfaces that enable personal fabrication for non-technical users, streamline the AM process by allowing real-time testing of the designed 3D models, and provide effective means of monitoring the AM process to improve the build quality of the product. I-nteract is a Visio-Haptic Mixed Reality (VHMR) system that enables real-time processing of human-centered spatio-temporal data acquired by vision (HoloLens) sensors and wearable sensors (position sensors for hand & fingers tracking) to provide visual augmented reality feedback (via HoloLens) and force feedback (via haptic gloves) to enable human interaction with physical and virtual world simultaneously. We demonstrated the efficacy of our system by implementing novel practical applications to improve the AM workflow. We developed a novel scan-based method for the real-time monitoring of AM processes. With the incorporation of haptics within the MR system, we demonstrated how I-nteract allows real-time interactions with both digital and physical (deformable/non-deformable) objects simultaneously to streamline the AM process by enabling virtual testing phase prior to the manufacturing phase. We proposed a novel 3D scanning method and implemented this novel strategy to design a customised orthopaedic cast for a human forearm. We also implemented interactions with the deformable objects so that the user can capture the elasticity along with the shape of a physical object to generate and simulate its digital twin. Furthermore, we introduced generative functionalities in the design phase of the AM workflow by using Constructive Solid Geometry (CSG) and integrating Deep Learning (DL) within the system to automate the parts of the design process that require expert knowledge. We tested the system with two types of generative Deep Neural Network (DNN)s to design customised 3D models of chairs and tables from their respective single-view 2D images captured via HoloLens, and by resizing the 3D models using hands in an MR environment with respect to the design constraints imposed by the physical workspace. Finally, in the context of improving the AM process to achieving stringent precision requirements by designing robust control strategies for the widespread adoption of AM technologies in the industrial sector, we proposed modal approximation based control strategies for the physical processes modelled by a reaction-diffusion equation. Heat flow is an important parameter of the AM process to achieve the high quality of the product. The systems where heat is produced and diffuses away from the heat production site are described by reaction-diffusion equations. First, we proposed state feedback control for a reaction-diffusion equation with a state delay in the reaction term. Then, to enhance the pragmatic feasibility of our proposed control design approach for practical application, we designed a finite-dimensional observer-based control strategy for the output feedback stabilization and setpoint regulation of a reaction-diffusion equation cascaded with an Ordinary Differential Equation (ODE). We showed that the control design strategies achieve both the exponential stabilization as well as the setpoint regulation of both the systems.
      169
  • Publication
    Digitally Intensive RF/Millimetre-Wave Frequency Generation Techniques
    (University College Dublin. School of Electrical and Electronic Engineering, 2022)
    Chen, Xi 
    ;
    0000-0002-2210-0075
    The advanced wireless communication standards (e.g., 5G) placed stringent specifications on the RF/mm-wave transceivers. As a main contributor to the total error vector magnitude (EVM), the local oscillator (LO) has been attracting many research interests. This thesis presents a number of techniques to address several major challenges in designing a digitally-intensive phase-locked loop (PLL) as an LO generator in RF/mm-wave transceivers. The first half of the thesis focuses on the design of the digitally controlled oscillator (DCO), which is the most important building block in a high-performance digitally-intensive PLL. More specifically, the issue of 1/$f^3$ phase noise (PN) in a DCO attracts extensive attention along the way to pursue ultralow phase noise (PN) DCO. Moreover, this problem is getting even worse with the CMOS transistors being scaled down and thereby causing serious flicker noise in the devices. To tackle this problem, we introduce a phase shift between the gate and drain nodes of the cross-coupled pair in a transformer-based resonance tank, to mitigate the detrimental effects of ill-behaved harmonics. The phase-shifting technique has been implemented and verified with a number of measured silicon chips across frequency bands. Another contribution is a method to resolve the rarely discussed $\pm90\degree$ mode ambiguity in mm-wave quadrature oscillators. Implemented by the transformer, the phase shift inserted in the quadrature coupling path makes the oscillator favor one mode over another. A phasor-based explanation is also included for a better intuitive understanding. In doing this, we constructed a theoretical framework based on phase shift to simultaneously reduce $1/f^3$ PN and resolve the mode ambiguity. The emphasis of the second half of the thesis is on the design of several other key building blocks in the PLL. Recently, fractional-$N$ operation based on the digital-to-time converter (DTC) is becoming increasingly popular, as it helps to push the border of the PLL figure-of-merit (FoM). Since the performance of low-jitter PLLs is usually limited by the in-band PN, the design of the reference path should be carefully considered. There are several blocks in the reference path, i.e., the crystal oscillator (XO), the low-noise clock buffer, and the DTC. Unfortunately, the power consumed by these building blocks is often forgotten and omitted in the total power calculation of the PLL. To improve energy efficiency, we propose a low noise reference path suitable for fractional-$N$ operation. With an integrated XO, the DTC takes advantage of the sinusoidal waveform and operates in the voltage domain. By eliminating the front-end buffer and optimizing the XO and the DTC together, a low-jitter, low-power clock with programmable delay can be obtained. Furthermore, to bring the mm-wave output frequency to a frequency close to the reference clock, a frequency divider chain is an integral element in high-frequency PLLs which typically burn a considerable power. In this thesis, we have verified a wide locking range (LR) in a low-power, high-division ratio ring-based injection-locked frequency divider (ILFD) with the support of an analysis based on impulse-sensitivity function (ISF).
      6
  • Publication
    Flicker Noise Upconversion and Reduction Mechanisms in RF/Millimeter-Wave Oscillators for 5G Communications
    (2019-09-19)
    Hu, Yizhe 
    The fifth generation (5G) cellular communications in millimeter-wave (mmW) bands (e.g., 28GHz) place very tough requirements on phase noise (PN) of local oscillators (LO). However, in the advanced CMOS technology (e.g., 28nm, 16nm, 7nm, ...), the intrinsic 1/f current noise of MOS transistor is increasingly worsening. It could adversely affect the PN of the LO significantly, especially the flicker PN, leading to a very high 1/f3 PN corner (usually exceeding 1 MHz), which is difficult to be attenuated by a mmW PLL. On the other hand, the current literature is full of conflicts and confusing theories about the flicker noise upconversion, with a large number of ambiguities in the RF range, let alone in the mmW range. Thus, lowering the 1/f3 PN and figuring out its actual mechanisms are highly desired for 5G mmW communications.
      957
  • Publication
    Frequency Control of Distributed Energy Resources Integrated into Low Voltage Distribution Network
    (University College Dublin. School of Electrical and Electronic Engineering, 2020)
    Ibrahim, Ismail 
    ;
    0000-0002-6744-8227
    The growth in the integration of converter interfaced renewable energy has reduced the system inertia, which threatens system stability due to high rate of change of frequency and frequency nadir issues unless steps are taken to mitigate it. There is a need to provide sufficient fast frequency response to maintain adequate inertia in the system. This thesis investigates the capabilities of a large population of distributed energy resources such as residential energy storage and heating loads to provide an emulated inertial response. There is a need to find improved ways to analyze, test and evaluate the new control strategies for the provision of inertial response. Real-time simulation with hardware in the loop provides a very promising approach for this which enables the coupling of real hardware with power system simulations thus enabling study of the real-time interactions between the hardware and control and the wider system. This thesis presents a real-time simulation platform with hardware in the loop aimed at providing a platform for the test and evaluation of new technologies and new control strategies for the integration of distributed energy resources. The distribution grid model used for the real-time simulation is based on distribution grid in the Manchester area. This network contains three feeders with 330 houses, 6350 nodes and three-phase, four-wire configuration distribution cables. The conventional on/off controlled demand response, when installed in a large number of loads require some coordination for stable operation of the power system. Also, it is not possible to incorporate inertia emulation techniques into the on-off controlled demand response. This thesis proposes an inertial emulation technique for heating loads, both resistive loads and heat pumps. The thesis presents the small-signal transfer functions, stability analysis, and aggregated response of a large population of virtual inertia controlled resistive heaters and heat pumps. Finally, the thesis presents an investigation of the control based on grid-following and grid-forming approach for a single-phase residential battery storage system for the provision of frequency support. The thesis presents the full switched, reduced order model and small-signal transfer function for single-phase grid following and grid forming energy storage converters with virtual inertia control. Then the thesis presents stability analysis and simulations of a large population of energy storage converters in the real-time simulation platform. There are no stability issues with the grid-following approach, but the grid forming approach has more limited stability range. The simulation results shows the interaction between frequency support with voltage, and the effect of controller settings on voltage and frequency support.
      92
  • Publication
    Frequency Control of Virtual Power Plants
    (University College Dublin. School of Electrical and Electronic Engineering, 2022)
    Zhong, Weilin 
    ;
    0000-0001-6737-4873
    The Virtual Power Plant (VPP) concept refers to the aggregation of Distributed Energy Resources (DERs) such as solar and wind power plants, Energy Storage Systems (ESSs), flexible loads, and communication networks, all coordinated to operate as a single generating unit. Using as starting point a comprehensive literature review of the VPP concept and its frequency regulation technologies, the thesis proposes a variety of frequency control and state estimation approaches of VPPs, as follows. First, the thesis studies the impact of coordinated frequency control of VPPs on power system transients, in which ESSs are utilized to provide fast frequency regulation. The thesis also proposes a simple yet effective coordinated control of DERs and ESSs able to integrate the total active power output of the DERs, and, thus, to improve the overall power system dynamic performance. The impact of topology on the primary frequency regulation of VPPs is also investigated. With this regard, two types of VPPs topologies are considered, that is, a topology where the DERs that compose the VPP are scattered all-over the transmission grid; and a topology where the DERs are all connected to the same distribution system that is connected to the rest of the transmission grid through a single bus. Next, the thesis proposes a control scheme to improve the dynamic response of power systems through the automatic regulators of converter-based DERs. In this scheme, both active and reactive power control of DERs are varied to regulate both frequency and voltage, as opposed to current practice where frequency and voltage controllers are decoupled. To properly compare the proposed control with conventional schemes, the thesis also defines a metric that captures the combined effect of frequency/voltage response at any given bus of the network. Finally, the thesis presents an on-line estimation method to track the equivalent, time-varying inertia as well as the fast frequency control droop gain provided by VPPs. The proposed method relies on the estimation of the rate of change of the active and reactive power at the point of connection of the VPP with the rest of the grid. It provides, as a byproduct, an estimation of the VPP’s internal equivalent reactance based on the voltage and reactive power variations at the point of connection. Throughout the thesis, the proposed techniques are duly validated through time domain simulations and Monte Carlo simulations, based on real-world network models that include stochastic processes as well as communication delays.
      8
  • Publication
    Fully Integrated Switched-Capacitor DC-DC Converter in All-Digital PLL for IoT Applications
    (University College Dublin. School of Electrical and Electronic Engineering, 2019-11-19)
    Pourmousavian, Naser 
    The development of Internet of Things (IoT) is driving research and innovation to connect our day-to-day ‘things’, such as wearable devices, wireless electronics, implantable sensors, and smart appliances. The ‘smart’ nodes in IoT applications generally comprise wireless communication blocks, power management units (PMUs), energy sources, digital signal processing, and sensors, and are often implemented as system-on-chip (SoC) solutions. Consequently, high power efficiency, low power consumption, small silicon area, and low cost are the main requirements for IoT SoC implementation. Several popular standards, such as Bluetooth low energy (BLE), are defined for IoT. The development of radios for IoT node devices has spurred research in ultra-low-power (ULP) all-digital phase-locked loops (ADPLLs) performing as local oscillators (LOs). The IoT concept entails stringent conditions on the size and weight of the battery. In spite of recent advancements, the IoT system lifetime is still limited by the power consumption of its radio, and in particular the LO. Consequently, this triggers inconvenient battery replacements, which limits their marketing attractiveness. The lifetime could be easily extended with larger batteries but that comes at a price of increased weight and size and it is clearly against the vision of IoT miniaturization. Energy harvesters can significantly extend the IoT lifetime up to the point of perpetual operation. Among them, solar cells have gained a significant popularity due to their high-power density and low cost. However, they typically provide low voltages, especially when operating indoors, often well below the typical supply of CMOS circuits. This is likely to degrade performance of important ADPLL building blocks. An inverter-based time-to-digital converter (TDC) is such an example. In this dissertation, we carry out research to implement an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5V supply which has never been done before. We demonstrate that while its digitally controlled oscillator (DCO) can run directly at 0.5 V, an internal switched-capacitor dc–dc converter could be employed to ‘double’ the supply voltage to all the digital circuitry and particularly to regulate the TDC supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage and temperature (PVT). The ADPLL supports 2-point modulation and forms a BLE transmitter realized in 28-nm CMOS. It maintains excellent in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86 ps while dissipating only 1.6mW at 40MHz reference. The power consumption reduces to 0.8mW during the BLE transmission when the DCO switches to open-loop. Furthermore, to go towards even lower voltages, we implement the first-ever deep sub-1V monolithic step-up dc–dc converter operating at 0.18–0.4V that outputs significant power for IoT with a peak power efficiency of 81.2% at 50 µW output power for the 0.18V input, and 87.1% at 300 µW output power for 0.4 V. It is implemented in 16-nm FinFET CMOS and uses a metal-oxide-semiconductor (MOS) transistor as a high-density flying capacitor for energy conversion. The capacitor is arranged in a self-biased deep N-well topology, which enhances the overall efficiency by 9.5%. An integrated time-to-digital converter (TDC) verifies the dc–dc output quality.
      782
  • Publication
    Impact of noise (auto)correlation on power system dynamic performance
    (University College Dublin. School of Electrical and Electronic Engineering, 2022)
    Adeen, Muhammad 
    ;
    0000-0002-9418-8539
    Non-deterministic loads and non-dispatchable renewable energy sources such as wind and photovoltaic are the major sources of random fluctuations and volatility in power systems. The techniques to account for the effects of random fluctuations on the transient behaviour of the power system have been developed and well-assessed in the literature. On the other hand, the analysis of impact of volatility on the power system short-term dynamic and transient behaviour has not been fully explored so far. For power system dynamic studies, volatility can be modelled as a fast-varying time-continuous stochastic process. Stochastic processes are formulated as Stochastic Differential Equations (SDEs). SDEs are then introduced into existing power system dynamic models to generate nonlinear Stochastic Differential Algebraic Equations (SDAEs). SDAEs are the fundamental tool, utilised in this thesis, to study the dynamic behaviour of the power system subjected to volatility. Stochastic processes have three distinct features, namely, drift, correlation, and diffusion. While the impact of the latter on the system dynamics has been studied widely that is not the case for the other two. The drift defines the variability of the process in time. Whereas the correlation is the degree of similarity between two processes. Thus, the question on what the impact of drift and correlation of the stochastic processes on the dynamic behaviour of the power system is and how to quantify it remains unanswered. This thesis aims at providing systematic and generalized methods based on data measurements to model correlation on stochastic processes and introduce them into power system dynamic studies. The thesis also provides a general technique to extract correlation from the measurement data. The methods provided in this thesis are independent of dimensions, timescales, drifts, and probability distributions of the processes. This allows for the inclusion of a wide range of sources of volatility into existing power system dynamic models and the study of their impact on power system dynamics without the need for any simplifications or modifications to the original system. On the other hand, the impact of the drift of the stochastic processes on the power system dynamic behaviour is studied through time- and frequency-domain analyses. The former involves the study of the impact of the drift of the stochastic processes on the power system variables in normal grid operation. Whereas the latter consists in the study of the dynamic interactions between the drift of the stochastic processes and the electro-mechanical oscillatory modes of the power system. The thesis also presents a direct method to assess the probability that a power system's physical limit is violated when modelling stochastic processes in normal grid operation. The accuracy and computational efficiency of the direct method is demonstrated using the bench-mark Irish system. Direct methods can only study a linearized system at stationary conditions. Whereas the detailed dynamic behaviour of the power system simulating stochastic processes, controller hard limits, saturations and system nonlinearities can only be studied using the nonlinear models, which do not have a closed form solution. For this reason, the analyses conducted in the entire thesis, except for the direct method, rely on time domain simulations. Several case studies utilising the Irish system are illustrated throughout the thesis to demonstrate the practical applications of the introduced methods to model and study the impact of correlated stochastic processes on the power system dynamic and transient security. As the modelling techniques presented in the thesis are general, based on measurement data and easy to implement in software tools. They are expected to be readily adopted by the system operators to ensure the security and stability of the power system in the presence of stochastic processes.
      66
  • Publication
    Investigation and Optimisation of Kinetic Energy Harvesters with Nonlinear Electromechanical Coupling Mechanisms
    (University College Dublin. School of Electrical and Electronic Engineering, 2022)
    Sokolov, Andrii 
    ;
    0000-0001-5655-115X
    This thesis applies various nonlinear analysis techniques to reconstruct the qualitative and quantitative characteristics of Kinetic Energy Harvesters (KEHs) and proposes methods to optimize them. Having the optimization of electromagnetic and electrostatic harvesters achieved, a concept of the near-limit KEH is introduced specifically on realistic patterns of motion. Chapter 2 gives a general review of the KEH field with regard to types of energy harvesting devices, the amount of power they can generate and their compatibility with different sensors. Chapter 3 contains a detailed description of modeling approaches for KEHs with various transduction mechanisms. It provides comprehensive information on how to model various interaction forces acting on the proof-mass of an KEH, particularly, dissipative forces and piece-wise stopper interactions. Finally, various techniques to model the dynamics of the system, such as numerical solutions of the motion equations, harmonic balance method and multiple scales method are shown in this chapter. Chapter 4 shows a successful application of the methods described in Chap. 3 to meso-scale KEHs with the electromagnetic transduction mechanism. A fast and reliable method of equivalent coils is used to solve for the magnetic field developed in such a system. Chapter 5 is focused on the problem of frequency up-conversion in KEHs with electrostatic transduction. Employing the technique shown in Chap. 3 on experimental resonance curves, we reproduce the waveforms of the mechanical motion of the proof-mass. By analyzing them in terms of higher harmonic, we discover the reason behind high-power generation at low frequencies in systems with up-conversion. The Concept of kinetic energy harvesting that is forced to move following the optimal trajectory for a given excitation is shown in Chapter 6. The main feature of the near-limit control of KEH is prediction of the next maximum-minimum pair in the external acceleration, and the corresponding control. The acceleration patterns of various human motion waveforms are measured and used as the possible external excitation to test Near-Limit Kinetic Energy Harvester (NLKEH). In addition, techniques to predict the next extremum in generic acceleration pattern are investigated. Finally, Chapter 7 summarizes the thesis and presents main conclusions.
      123
  • Publication
    Low-Complexity Digital Predistortion for 5G Massive MIMO and Handset Transmitters
    (University College Dublin. School of Electrical and Electronic Engineering, 2022)
    Wang, Xiaoyu 
    The demand for new wireless communication systems to support high mobility and low latency necessitates a rethink of the architecture of wireless communication systems as well as the design of their key components. This thesis presents several novel techniques to solve the major challenges in digital predistortion (DPD) for millimeter wave multi-input multi-output (MIMO) and handset transmitters to lower the hardware cost and computational complexity of the fifth generation (5G) communication systems. The first part of the thesis focuses on the architecture of the MIMO DPD solution for 5G transmitters. To extract DPD model coefficients, a feedback data acquisition path is required. In conventional single-input single-output (SISO) systems, the output is usually acquired directly from the power amplifier (PA) with a coupler. In massive MIMO systems, the number of RF chains is large. Using dedicated feedback paths for each PA separately is not feasible. To lower the hardware cost, a novel data acquisition scheme is proposed to obtain the output signals in far field over the air (OTA) using a single antenna and feedback loop, and then reconstruct the output of each PA. Simulation and experimental results demonstrate that the proposed OTA data acquisition can accurately reconstruct the output of each PA in the MIMO systems and the DPD solutions derived from the reconstructed data can successfully linearize the nonlinear MIMO transmitters. In the multi-user scenario, the nonlinearity of the transmitters varies with the movement of user equipments (UEs), and the DPD model coefficients need to be updated accordingly. To meet the requirement of high mobility, the complexity of the system update must be low. In the second part of the thesis, we present a new DPD system, where DPD model can be updated fast and accurately without capturing PA output or applying costly model extraction algorithms. In the proposed method, nonlinear characteristics of the PA are encoded into low-dimensional PA features using feature extraction algorithms. To identify DPD model coefficients, PA features are extracted first and the DPD model coefficients are then generated directly by DPD generator with PA features. Experimental results show that the proposed DPD solution can linearize PA with very low complexity compared to that using the conventional solutions. Finally, the focus shifts to handset transmitters. Conventionally, DPD is usually deployed for high power base stations. With the continuously increasing bandwidth, DPD may also be required for handset PAs in 5G communication systems. Different from the models used for base stations, DPD model for handset PAs must have very low complexity because of the stringent power budget limit. At the same time, the tolerance for load mismatch must also be considered. The third part of the thesis analyzes the characteristics of handset PAs with load mismatch and introduces a low-complexity DPD model based on magnitude-selective affine (MSA) function. Experimental results demonstrate that the extended MSA (EMSA) model shows better linearization performance while keeping much lower complexity than the conventional DPD models.
      9