Now showing 1 - 2 of 2
  • Publication
    A Novel Concurrent Error Detection Technique for the Fast Fourier Transform
    (The Institution of Engineering and Technology, 2012-06) ; ;
    A novel Concurrent Error Detection technique for the Fast Fourier Transform (FFT) is proposed in this paper. The technique is similar to the conventional Sum of Squares (SOS) approach but is of lower computational complexity. Complexity reduction is achieved by checking the FFTs of two data blocks in a single calculation. The technique is based on checking the equivalence of the results of time and frequency domain calculations of the first sample of the circular convolution of the two blocks. In the case of error, the FFTs of both blocks must be recomputed. Assuming that errors are rare, this additional cost has negligible impact on the average number of operations per block.
  • Publication
    Low Complexity Concurrent Error Detection for Complex Multiplication
    This paper studies the problem of designing a low complexity Concurrent Error Detection (CED) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits. Five novel CED architectures are proposed and their computational complexity, area, and delay evaluated in several circuit implementations. The most efficient architecture proposed reduces the number of gates required by up to 30 percent when compared with a conventional CED architecture based on Dual Modular Redundancy. Compared to a Residue Code CED scheme, the area of the proposed architectures is larger. However, for some of the proposed CEDs delay is significantly lower with reductions exceeding 30 percent in some configurations.
      283ScopusĀ© Citations 12