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- PublicationLow Complexity Concurrent Error Detection for Complex MultiplicationThis paper studies the problem of designing a low complexity Concurrent Error Detection (CED) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits. Five novel CED architectures are proposed and their computational complexity, area, and delay evaluated in several circuit implementations. The most efficient architecture proposed reduces the number of gates required by up to 30 percent when compared with a conventional CED architecture based on Dual Modular Redundancy. Compared to a Residue Code CED scheme, the area of the proposed architectures is larger. However, for some of the proposed CEDs delay is significantly lower with reductions exceeding 30 percent in some configurations.
314Scopus© Citations 12
- PublicationArea efficient concurrent error detection and correction for parallel filtersIn modern signal processing circuits, it is common to find several filters operating in parallel. In this letter, we propose an area efficient technique to detect and correct single errors occurring in pairs of parallel filters that have either the same input data or the same impulse response. The technique uses a primary implementation comprised of two independent filters and a redundant implementation that shares input data between both filters so as to detect and correct errors. Herein, the area cost of the proposed scheme is shown to be slightly more than double that of the unprotected filter, whereas the conventional Triple Modular Redundancy solution requires an area three times that of the unprotected filter.
433Scopus© Citations 19