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Maestro, J.A.
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Maestro, J.A.
Official Name
Maestro, J.A.
Research Output
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Publication
Increasing the MTU size for Energy Efficiency in Ethernet
2010-06-23, Reviriego, P., Sanchez-Macian, A., Maestro, J.A., Bleakley, Chris J.
The commonly used Maximum Transfer Unit (MTU) on the Internet has
remained unchanged for many years at around 1500 bytes due mainly to
backward compatibility issues. This is in contrast with link data rate,
which has increased by several orders of magnitude. In this paper, a new
advantage of using larger MTUs is introduced, namely Energy Efficiency.
In wire-line environments, the link power consumption is generally
roughly independent of the number of frames that are transmitted
resulting in a poor energy efficiency. This will change with the
development of standards like IEEE 802.3az, Energy Efficient Ethernet.
This new standard allows a link to enter a low power mode when there are
no frames to transmit therefore making power consumption almost
proportional to the link load. In this context the use of larger MTUs
minimizes the number of transitions between the active and low power
modes thereby improving energy efficiency. The benefits of using larger
MTUs in terms of energy efficiency are analyzed in this paper.
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Publication
Efficient Concurrent Error Detection and Correction of Soft Errors in NTT-based Convolutions
2009-06, O'Donnell, Anne, Bleakley, Chris J., Reviriego, P., Maestro, J.A.
A system for soft error detection and correction is proposed for digital Integrated Circuit (IC) implementation of convolution. The convolution is implemented in a Residue NumberSystem using Fermat Number Theoretic Transforms. The flexibility afforded by the Modified Overlap Technique in allowing transforms of differing lengths in a convolution makes it possible to easily detect and correct soft errors by means of a Single Redundant Channel and pattern matching technique. The proposed system gives area reductions in the majority of cases examined, when compared with Triple Modular Redundancy. In the case of large (e.g. 28 and 32 bit) word lengths, the proposed system provides area reductions of up to 30%.
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Publication
A Novel Concurrent Error Detection Technique for the Fast Fourier Transform
2012-06, Reviriego, P., Bleakley, Chris J., Maestro, J.A.
A novel Concurrent Error Detection technique for the Fast Fourier Transform (FFT) is proposed in this paper. The technique is similar to the conventional Sum of Squares (SOS) approach but is of lower computational complexity. Complexity reduction is achieved by checking the FFTs of two data blocks in a single calculation. The technique is based on checking the equivalence of the results of time and frequency domain calculations of the first sample of the circular convolution of the two blocks. In the case of error, the FFTs of both blocks must be recomputed. Assuming that errors are rare, this additional cost has negligible impact on the average number of operations per block.