Now showing 1 - 10 of 11
- PublicationReliability Analysis of Memories Protected with BICS and a per-Word Parity BitThis paper presents an analysis of the reliability of memories protected with Built-in Current Sensors (BICS) and a per-word parity bit when exposed to Single Event Upsets (SEUs). Reliability is characterized by Mean Time to Failure (MTTF) for which two analytic models are proposed. A simple model, similar to the one traditionally used for memories protected with scrubbing, is proposed for the low error rate case. A more complex Markov model is proposed for the high error rate case. The accuracy of the models is checked using a wide set of simulations. The results presented in this paper allow fast estimation of MTTF enabling design of optimal memory configurations to meet specified MTTF goals at minimum cost. Additionally the power consumption of memories protected with BICS is compared to that of memories using scrubbing in terms of the number of read cycles needed in both configurations.
260Scopus© Citations 6
- PublicationArea efficient concurrent error detection and correction for parallel filtersIn modern signal processing circuits, it is common to find several filters operating in parallel. In this letter, we propose an area efficient technique to detect and correct single errors occurring in pairs of parallel filters that have either the same input data or the same impulse response. The technique uses a primary implementation comprised of two independent filters and a redundant implementation that shares input data between both filters so as to detect and correct errors. Herein, the area cost of the proposed scheme is shown to be slightly more than double that of the unprotected filter, whereas the conventional Triple Modular Redundancy solution requires an area three times that of the unprotected filter.
434Scopus© Citations 19
- PublicationDiverse Double Modular Redundancy: A New Direction for Soft Error Detection and CorrectionSoft errors are becoming an important issue for deep submicron technologies. To protect circuits against soft errors, designers routinely introduce modular redundancy to detect and correct these errors. A commonly used technique, Double Modular Redundancy (DMR) involves duplication of the basic module. Conventionally, DMR only allows error detection since voting cannot be used to determine the module in error. Recently, however, it has been found that DMR can, for some circuits, be enhanced to provide soft error correction as well as detection. The general approach, DDMR (Diverse DMR), relies on introducing design diversity between the original and redundant modules so that they produce different error patterns when a soft error occurs. The module in error can be found by examining these patterns. Herein, the generalized approach is described. A number of techniques for producing diverse designs with distinct error patterns are identified and illustrated with examples. New DDMR solutions are presented and finally, the future direction of DDMR research is discussed.
451Scopus© Citations 26
- PublicationSignal Shaping Dual Modular Redundancy for Soft Error Tolerant Finite Impulse Response FiltersA technique to protect finite impulse response (FIR) filters against soft errors is presented. The approach is based on the use of two copies of the FIR filter. In one of the copies, preprocessing of the input and a postprocessing of the output are added. In the event of a soft error, the outputs of the filters differ or mismatch for one or more samples. The additional processing introduced in the second copy of the filter ensures that the mismatch patterns are unique to each copy. Hence, the copy in error can be identified and the output of the other copy selected as the final error protected filter output. The proposed scheme can efficiently correct isolated soft errors at lower cost than general techniques, such as triple modular redundancy.
309Scopus© Citations 9
- PublicationLow Complexity Concurrent Error Detection for Complex MultiplicationThis paper studies the problem of designing a low complexity Concurrent Error Detection (CED) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits. Five novel CED architectures are proposed and their computational complexity, area, and delay evaluated in several circuit implementations. The most efficient architecture proposed reduces the number of gates required by up to 30 percent when compared with a conventional CED architecture based on Dual Modular Redundancy. Compared to a Residue Code CED scheme, the area of the proposed architectures is larger. However, for some of the proposed CEDs delay is significantly lower with reductions exceeding 30 percent in some configurations.
314Scopus© Citations 12
- PublicationLow-Complexity Concurrent Error Detection for Convolution with Fast Fourier TransformsIn this paper, a novel low-complexity Concurrent Error Detection (CED) technique for Fast Fourier Transform-based convolution is proposed. The technique is based on checking the equivalence of the results of time and frequency domain calculations of the first sample of the circular convolution of the two convolution input blocks and of two consecutive output blocks. The approach provides low computational complexity since it re-uses the results of the convolution computation for CED checking. Hence, the number of extra calculations needed purely for CED is significantly reduced. When compared with a conventional Sum Of Squares - Dual Modular Redundancy technique, the proposal provides similar error coverage for isolated soft errors at significantly reduced computational complexity. For an input sequence consisting of complex numbers, the proposal reduces the number of real multiplications required for CED in adaptive and fixed filters by 60% and 45%, respectively. For input sequences consisting of real numbers, the reductions are 66% and 54%, respectively.
- PublicationEfficient Concurrent Error Detection and Correction of Soft Errors in NTT-based ConvolutionsA system for soft error detection and correction is proposed for digital Integrated Circuit (IC) implementation of convolution. The convolution is implemented in a Residue NumberSystem using Fermat Number Theoretic Transforms. The flexibility afforded by the Modified Overlap Technique in allowing transforms of differing lengths in a convolution makes it possible to easily detect and correct soft errors by means of a Single Redundant Channel and pattern matching technique. The proposed system gives area reductions in the majority of cases examined, when compared with Triple Modular Redundancy. In the case of large (e.g. 28 and 32 bit) word lengths, the proposed system provides area reductions of up to 30%.
- PublicationIncreasing the MTU size for Energy Efficiency in EthernetThe commonly used Maximum Transfer Unit (MTU) on the Internet has remained unchanged for many years at around 1500 bytes due mainly to backward compatibility issues. This is in contrast with link data rate, which has increased by several orders of magnitude. In this paper, a new advantage of using larger MTUs is introduced, namely Energy Efficiency. In wire-line environments, the link power consumption is generally roughly independent of the number of frames that are transmitted resulting in a poor energy efficiency. This will change with the development of standards like IEEE 802.3az, Energy Efficient Ethernet. This new standard allows a link to enter a low power mode when there are no frames to transmit therefore making power consumption almost proportional to the link load. In this context the use of larger MTUs minimizes the number of transitions between the active and low power modes thereby improving energy efficiency. The benefits of using larger MTUs in terms of energy efficiency are analyzed in this paper.
344Scopus© Citations 1
- PublicationStructural DMR: A Technique for Implementation of Soft Error Tolerant FIR FiltersIn this brief, an efficient technique for implementation of soft-error-tolerant finite impulse response (FIR) filters is presented. The proposed technique uses two implementations of the basic filter with different structures operating in parallel. A soft error occurring in either filter causes the outputs of the filters to differ, or mismatch, for at least one sample. The filters are specifically designed so that, when a soft error occurs, they produce distinct error patterns at the filter output. An error detection circuit monitors the basic filter outputs and identifies any mismatches. An error correction circuit determines which filter is in error based on the mismatch pattern and selects the error-free filter result as the output of the overall error-protected system. This technique is referred to as structural dual modular redundancy (DMR) since it enhances traditional DMR to provide error correction, as well as error detection, by means of filter modules with different structures. The proposed technique has been implemented and evaluated. The system achieves a soft error correction rate of close to 100% for isolated single soft errors and has a logic complexity significantly less than that of conventional triple modular redundancy.
489Scopus© Citations 26
- PublicationImplications of energy efficient Ethernet for hubs and switchesThe efficient use of energy in communications is an area of growing interest. Until recently energy efficiency received little attention in most wireline communications standards and implementations. In many cases, the transmitter and receiver operate at full power, even when no data is being sent. This is the case in most wireline Ethernet standards that results in a considerable waste of energy. Efforts are now underway to develop new standards, such as energy efficient Ethernet, with the aim of reducing energy consumption. The changes introduced by energy efficient Ethernet have different implications for each network element. The implications for hubs are different to those for switches. These implications are analysed in this paper. It is shown that the adoption of the new standard will make hubs less energy efficient than switches. The implications studied in this paper illustrate the potential impact of energy efficient Ethernet on Ethernet networks.
373Scopus© Citations 2