Now showing 1 - 5 of 5
  • Publication
    Semianalytical model for high speed analysis of all-digital PLL clock-generating networks
    In this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with experimental measurements of a 65nm CMOS All-Digital Phase-Locked Loop Network.
      420Scopus© Citations 3
  • Publication
    Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology
    This brief presents an active distributed clock generator for manycore systems-on-chip consisting of a 10×10 network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequency range of 700–840 MHz at VDD=1.1 V. The network is highly robust against VDD variations. An energy cost of 2.7 μW /MHz per node is 7 times lower than that in analog implementations of similar architectures and is twice lower than that in conventional H-tree architectures. This is the largest on-chip all-digital phase-locked loop network ever implemented. With clock generation nodes linked only locally, this solution is proven to be scalable. The presented clock generation network does not require any external reference, except for the start-up frequency selection, generating a synchronized signal in fully autonomous mode and maintaining frequency stability within 0.09% during 1700 seconds. Such a network of frequency and phase synchronized oscillators can be used as a source for local clocking areas.
      413Scopus© Citations 4
  • Publication
    Limit on Converted Power in Resonant Electrostatic Vibration Energy Harvesters
    Based on the formal analysis of a resonant electrostatic vibration energy harvester operating in constant-charge mode with a gap-closing transducer, we show that the system displays universal behaviour patterns. In this paper, we treat the harvester as a nonlinear forced oscillator and bound the area of control parameters where the system displays regular harmonic oscillations allowing the conditioning circuit to operate in the most effective mode. Before the system exhibits irregular behaviour, there exists a universal optimal value of normalised converted power regardless of the system design and control parameters.
    Scopus© Citations 17  504
  • Publication
    Generation of a Clocking Signal in Synchronized All-Digital PLL Networks
    In this brief, we propose a discrete-time framework for the modeling and studying of all-digital phase-locked loop (ADPLL) networks with applications in clock-generating systems. The framework is based on a set of nonlinear stochastic iterating maps and allows us to study a distributed ADPLL network of arbitrary topology. We determine the optimal set of control parameters for the reliable synchronous clocking regime, taking into account the intrinsic noise from both local and reference oscillators. The simulation results demonstrate very good agreement with experimental measurements of a 65-nm CMOS ADPLL network. This brief shows that an ADPLL network can be synchronized both in frequency and phase. We show that for a large Cartesian network the average network jitter increases insignificantly with the size of the system.
      423Scopus© Citations 10
  • Publication
    Bifurcation Scenarios in Electrostatic Vibration Energy Harvesters
    In this paper, we present numerical bifurcation analysis of an electrostatic vibration energy harvester operating in constant-charge mode and using the in-plane gap closing transducer. We show how the system can be represented as a nonlinear oscillator and analysed using methods of nonlinear dynamics. We verify previous analytical theories and explain the behaviour of these energy harvesters, particularly in the regime between the first period doubling bifurcation and chaos.
      304