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Galayko, Dimitri
Preferred name
Galayko, Dimitri
Official Name
Galayko, Dimitri
Research Output
Now showing 1 - 4 of 4
- PublicationSemianalytical model for high speed analysis of all-digital PLL clock-generating networksIn this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with experimental measurements of a 65nm CMOS All-Digital Phase-Locked Loop Network.
424Scopus© Citations 3 - PublicationGeneration of a Clocking Signal in Synchronized All-Digital PLL NetworksIn this brief, we propose a discrete-time framework for the modeling and studying of all-digital phase-locked loop (ADPLL) networks with applications in clock-generating systems. The framework is based on a set of nonlinear stochastic iterating maps and allows us to study a distributed ADPLL network of arbitrary topology. We determine the optimal set of control parameters for the reliable synchronous clocking regime, taking into account the intrinsic noise from both local and reference oscillators. The simulation results demonstrate very good agreement with experimental measurements of a 65-nm CMOS ADPLL network. This brief shows that an ADPLL network can be synchronized both in frequency and phase. We show that for a large Cartesian network the average network jitter increases insignificantly with the size of the system.
426Scopus© Citations 10 - PublicationSynchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS TechnologyThis brief presents an active distributed clock generator for manycore systems-on-chip consisting of a 10×10 network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequency range of 700–840 MHz at VDD=1.1 V. The network is highly robust against VDD variations. An energy cost of 2.7 μW /MHz per node is 7 times lower than that in analog implementations of similar architectures and is twice lower than that in conventional H-tree architectures. This is the largest on-chip all-digital phase-locked loop network ever implemented. With clock generation nodes linked only locally, this solution is proven to be scalable. The presented clock generation network does not require any external reference, except for the start-up frequency selection, generating a synchronized signal in fully autonomous mode and maintaining frequency stability within 0.09% during 1700 seconds. Such a network of frequency and phase synchronized oscillators can be used as a source for local clocking areas.
414Scopus© Citations 4 - PublicationAveraging Techniques for the Analysis of Event Driven Models of All Digital PLLsIn this paper, we introduce a statistical approach for studying a special class of nonlinear dynamical systems such as ADPLLs and ADPLL networks, where the process driving the adjustment of the DCO frequency can be seen as ΣΔ modulation. We showed that, by applying the Frobenius-Perron operator to the governing equation, it is possible to find the invariant probability density which is valid for dynamically changing input of ΣΔ modulator. By using this, we show that the average behaviour of the corresponding complex system can be dramatically simplified and studied analytically.
437Scopus© Citations 2