Now showing 1 - 7 of 7
- PublicationA 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOSThis paper introduces a phase shifter based on switched filters for mm-wave 5G MIMO transmitters. It is realized in 22 nm FD-SOI CMOS and exploits the use of back-gate biasing. The new approach features strong tolerance to process, voltage and temperature (PVT) variations and thus can maintain low phase error with fine phase tuning capability supporting a large bandwidth. Measurement results show that the 4-bit phase shifter achieves 3.5° rms phase error at 28 GHz. The proposed phase shifter can maintain <5° of the worst-case rms phase error when operating across 24 to 29.5 GHz resulting in 20.56% fractional bandwidth which is the largest among the published switched-filter phase shifters to date.
57Scopus© Citations 1
- PublicationA 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOSThis paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.
571Scopus© Citations 12
- PublicationIntuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased OscillatorsThis brief aims to intuitively explain and numeri- cally verify the observed phenomenon of flicker noise reduction in oscillators of reduced conduction angle (i.e., in class-C), which has been presented in literature but never properly explained. The flicker phase noise in a voltage-biased oscillator capable of operating in class-B and class-C is compared and numerically verified using a commercial simulation model of TSMC 28-nm CMOS. We illustrate how narrowing the conduction angle can suppress the 1/f noise up-conversion by decreasing 1/f noise exposure to the asymmetric rising and falling edges of oscillation waveform. The effects of implicit common-mode tank in the class- C operation is also discussed. We further clarify ambiguities among several simulation methods of impulse sensitivity function (ISF) based on periodic small-signal analysis (PAC or PXF), which is a key tool in understanding the flicker noise up- conversion. A clearer ISF simulation method based on positive sidebands of PXF is proposed.
406Scopus© Citations 18
- PublicationA 30-GHz Class-F23 Oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz l/f3 CornerThis paper presents a mmW frequency generation stage aimed at minimizing phase noise via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A second-harmonic tank resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for shortest and well controlled common-mode current return path. Class-F operation with third-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10 GHz tank at the 30 GHz frequency generation while providing implicit divide-by-3 functionality. The proposed 27.3-31.2 GHz oscillator is implemented in 28-nm CMOS. It achieves phase noise of-106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dB at 27.3GHz. Its flicker phase-noise (1/f3) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.
301Scopus© Citations 10
- PublicationCryogenic Low-Drop-Out Regulators Fully Integrated with Quantum Dot Array in 22-nm FD-SOI CMOSThis brief presents two monolithically integrated output-capacitor-less ("caples") low-drop-out (LDO) linear regulators implemented in 22-nm fully depleted silicon-on-insulator (FD-SOI) to support on-die scalable CMOS charge-based quantum processing unit (QPU). The proposed LDOs are used to regulate 0.8 V and 1.5 V input voltages for the programmable capacitive digital-to-analog converter (CDAC) and single-electron detector, respectively. Measured results show that both LDOs can maintain their respective output voltages with a maximum deviation <2% from ~270 K down to ~ 3.7 K.
84Scopus© Citations 1
- PublicationA Low Profile Highly Isolated Phased Array MIMO Antenna System for 5G Applications at 28 GHzThis paper presents a highly isolated phased array antenna system for 5G applications at 28 GHz. The antenna array is formed by 1x8 microstrip antipodal exponential tapered slot antennas each connected to CMOS phase shifters with wire bonds for electrical beam steering. At 28 GHz, the mutual coupling between the antenna elements are lower than -30 dB while the envelope correlation between the ports is less than 0.1. The single antenna array element was fabricated on 20 mil thick Rogers 4003 substrate and the phase shifter was fabricated in 22 nm FD-SOI CMOS. The simulated and measured results of the single antenna element along with the integrated phase shifter are presented together with the simulation results of the overall system.
115Scopus© Citations 1
- PublicationA Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return PathThis paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A 2nd-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10-GHz tank at the 30-GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors, and it is numerically verified against foundry models. The proposed 27.3- to 31.2-GHz oscillator is implemented in TSMC 28-nm CMOS. It achieves PN of -106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dBc/Hz at 27.3 GHz. Its flicker phase-noise (1/f3) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.
302Scopus© Citations 73