Now showing 1 - 2 of 2
  • Publication
    Low-Power TinyOS Tuned Processor Platform for Wireless Sensor Network Motes
    (Association for Computing Machinery (ACM), 2010-05-03) ; ;
    In this article we describe a low power processor platform for use in Wireless Sensor Network (WSN) nodes (motes). WSN motes are small, battery-powered devices comprised of a processor, sensors, and a Radio Frequency transceiver. It is expected that WSNs consisting of large numbers of motes will offer long-term, distributed monitoring, and control of real-world equipment and phenomena. A key requirement for these applications is long battery life. We investigate a processor platform architecture based on an application-specific programmable processor core, System-On-Chip bus, and a hardware accelerator. The architecture improves on the energy consumption of a conventional microprocessor design by tuning the architecture for a suite of TinyOS based WSN applications. The tuning method used minimizes changes to the Instruction Set Architecture facilitating rapid software migration to the new platform. The processor platform was implemented and validated in an FPGA-based WSN mote. The benefits of the approach in terms of energy consumption are estimated to be a reduction of 48% for ASIC implementation relative to a conventional programmable processor for a typical TinyOS application suite without use of voltage scaling.
      461Scopus© Citations 4
  • Publication
    GALS SoC Interconnect Bus for Wireless Sensor Network Processor Platforms
    (Association for Computing Machinery, 2007-03-13) ; ;
    The purpose of this paper is to present a new System-on-Chip bus designed for the application specific requirements of Wireless Sensor Network (WSN) platforms. The bus is designed to support Globally Asynchronous Locally Synchronous (GALS) systems. The bus is multi-rate with delay tolerance to support Dynamic Voltage and Frequency Scaled (DVFS) sub-systems. Unlike traditional buses, the sub-systems operate as peers, rather than as master-slaves. Lowpower features include clock gating when inactive and burst transfers. The bus supports up to 255 interconnected resources.
      320Scopus© Citations 7