Now showing 1 - 10 of 35
  • Publication
    Frequency quantization in first-order digital phase-locked loops with frequency-modulated input
    Frequency granularity in a digital phase-locked loop arises from quantization in the number-controlled oscillator which prevents the loop from locking exactly onto its reference signal and introduces unwanted phase jitter. Based on a nonlinear analysis of trajectories in the phase space, we have recently investigated the effect of frequency quantization in a first-order loop with a frequency-modulated input signal and have derived useful bounds on the steady-state phase jitter excursion. In this paper, we continue that work and derive the maximum modulation amplitude such that loop cycle slipping is avoided. We also examine in detail the loop behavior in acquiring phase-lock.
      218
  • Publication
    Dielectric charge control in electrostatic MEMS positioners / varactors
    A new dynamical closed-loop method is proposed to control dielectric charging in capacitive MEMS positioners/ varactors for enhanced reliability and robustness. Instead of adjusting the magnitude of the control voltage to compensate the drift caused by the dielectric charge, the method uses a feedback loop to maintain it at a desired level: the device capacitance is periodically sampled and bipolar pulses of constant magnitude are applied. Specific models describing the dynamics of charge and a control map are introduced. Validation of the proposed method is accomplished both through discrete-time simulations and with experiments using MEMS devices that suffer from dielectric charging.
      692Scopus© Citations 23
  • Publication
    Excitation of multiple spatial modes of a MEMS cantilever in the pulsed digital oscillator
    The aim of this paper is to apply an approach that will allow us to consider different mechanical modes of a MEMS cantilever in the form of separate mass-spring-damper equations with the appropriate form of an external driving. In the paper, we focus on a specific MEMS cantilever and use a Pulsed Digital Oscillator (PDO) to keep self-sustained oscillations of the mechanical structure. By applying the order-reduction procedure to a partial differential equation that describes the transversal deflections, we obtain a system of coupled ordinary differential equations that describes the excitation of multiple spatial modes. On the basis of these ordinary differential equations, we formulate a set of iterative maps to describe the evolution of the modes between two sampling events. The numerical simulations we present are focused on the most common case when the first two mechanical modes are taken into consideration
      342
  • Publication
    Capacitive Energy Conversion with Circuits Implementing a Rectangular Charge-Voltage Cycle Part 1: Analysis of the Electrical Domain
    Capacitive kinetic energy harvesters (KEH) employ conditioning circuits which achieve a dynamic biasing of the transducer's variable capacitor. This paper, composed of two articles Part 1 and Part 2, proposes a unified theory describing electrical and electromechanical properties of an important and wide class of conditioning circuits: those implementing a rectangular charge-voltage cycle. The article Part 1 introduces a basic configuration of conditioning circuit implementing an ideal rectangular QV cycle, and discusses its known practical implementations: the Roundy charge pump with different flyback mechanisms, and configurations based on the Bennet's doubler. In Part 1, the analysis is done in the electrical domain, without accounting for electromechanical coupling, while in Part 2, the full electromechanical system is analyzed. An optimization approach common to all configurations is proposed. A comparison is made between different topologies and operation modes, based on the maximal energy converted in one cycle under similar electrical and mechanical conditions. The last section discusses practical implementation of circuits with smart and adaptive behavior, and presents experimental results obtained with state-of-the art MEMS capacitive KEH devices.
      486Scopus© Citations 39
  • Publication
    Phase jitter dynamics of first-order digital phase-locked loops with frequency-modulated input
    Inherent to digital phase-locked loops is frequency quantization in the number-controlled oscillator which prevents the loop from locking exactly onto its reference signal and introduces unwanted phase jitter. This paper investigates the effect of frequency quantization in a first-order loop with a frequency-modulated input signal. Using tools of nonlinear dynamics, we show that, depending on the modulation amplitude, trajectories in the phase space eventually fall into either an invariant region or a trapping region, the boundaries of which give useful bounds on the steady-state phase jitter excursion. We also derive a sufficient condition for the maximum modulation amplitude to prevent loop cycle slipping.
    Scopus© Citations 2  360
  • Publication
    Steady-State Oscillations in Resonant Electrostatic Vibration Energy Harvesters
    In this paper, we present a formal analysis and description of the steady-state behavior of an electrostatic vibration energy harvester operating in constant-charge mode and using different types of electromechanical transducers. The method predicts parameter values required to start oscillations, allows a study of the dynamics of the transient process, and provides a rigorous description of the system, necessary for further investigation of the related nonlinear phenomena and for the optimisation of converted power. We show how the system can be presented as a nonlinear oscillator and be analysed by the multiple scales method, a type of perturbation technique. We analyse two the most common cases of the transducer geometry and find the amplitude and the phase of steady-state oscillations as functions of parameters. The analytical predictions are shown to be in good agreement with the results obtained by behavioural modeling.
    Scopus© Citations 32  711
  • Publication
    Semianalytical model for high speed analysis of all-digital PLL clock-generating networks
    In this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with experimental measurements of a 65nm CMOS All-Digital Phase-Locked Loop Network.
      420Scopus© Citations 3
  • Publication
    Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops
    (IEEE, 2009-05-24) ;
    Recently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional charge-pump-based analog PLLs. This paper is concerned with a class of DPLLs employing a binary-quantized phase detector, referred to as bangbang PLLs (BBPLLs). They are widely used in clock and data recovery circuits and have recently been implemented as digital BBPLLs for high-bandwidth synthesis. Given that a DPLL implementation typically suffers from (excess) loop delay, this paper investigates the combined effect of loop delay and reference clock jitter in a first-order digital BBPLL. To statistically characterize the loop’s timing jitter we formulate it as a discrete-time vector Markov process and numerically solve the associated Chapman-Kolmogorov equation. This allows us to compute the timing jitter probability density function in steady-state and to evaluate the jitter performance (timing offset and RMS timing jitter) for varying loop detuning, RMS reference clock jitter and loop delay.
    Scopus© Citations 5  436
  • Publication
    Mode-locking in a network of kuramoto-like oscillators
    In this paper we consider a network of phase oscillators. We develop the equations that model the time evolution of the phase of each oscillator in the network. The oscillator represents a modified Kuramoto oscillator and in this study we discuss how these modifications are obtained. In the context of this study, we use this network to model a network of PLLs for distributed clock applications. We analyse analytically and numerically the synchronisation modes of this system for different types of the coupling function. We show that depending on the properties of the coupling function, the network displays either multiple coexisting synchronisation modes or only a single synchronisation mode. While in the context of clock generation, multiple synchronisation modes coexisting in the system at the same parameters are a parasitic phenomenon. However in the context of other application such as associative memory models, mode-locking can be seen a useful phenomenon. The results provide a deeper understanding of globally synchronised clock networks with applications in microprocessor design.
    Scopus© Citations 2  399
  • Publication
    Limit Cycle Behavior in a Class-AB Second-Order Square Root Domain Filter
    This paper shows how an unwanted limit cycle can be exhibited by a second-order CMOS companding filter. The filter employs the quasi-quadratic law of the MOS transistor in strong inversion and saturation to achieve compression together with a Class-AB topology to extend the dynamic range. In the zero-input case, the filter operates in the manner expected of an externally-linear circuit. However, when a standard linear IC design technique is applied to it, unwanted zero-input sustained oscillations may be observed. Simulations from PSpice and measurement results from a semi-custom realization in a 0.8μm CMOS process are used to explore this behavior. This work highlights an aspect of the behavior of such filters that must be taken into account by analog designers.
    Scopus© Citations 2  665