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Feely, Orla
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Feely, Orla
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Feely, Orla
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- PublicationBinary phase detector gain in bang-bang phase-locked loops with DCO jitterBang-bang phase-locked loops (BBPLLs) are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In the presence of jitter, the nonlinear loop is typically analyzed by linearizing the BPD and applying linear transfer functions in the analysis. In contrast to a linear PD, the linearized gain of a BPD depends on the rms jitter and the type of jitter (either non-accumulative or accumulative). Previous works considered the case of nonaccumulative reference clock jitter and showed that the BPD gain is inversely proportional to the rms jitter when the latter is small or large. In this brief we consider the case of accumulative DCO jitter and derive an asymptotic closed-form expression for the BPD gain which becomes exact in the limit of small and large jitter. Contrary to the reference clock jitter case, the BPD gain is constant for small DCO jitter and is inversely proportional to the square of jitter for large DCO jitter; in the latter case, the timing jitter has a normal-Laplace distribution.
1697Scopus© Citations 14 - PublicationInvestigation of first-order digital bang-bang phase-locked loops with reference clock jitterBang-bang phase-locked loops (BBPLLs) are a class of PLLs with a binary-quantized phase detector (BPD). They are widely used in clock and data recovery circuits and have recently been implemented as digital BBPLLs for high-bandwidth synthesis. This paper investigates a first-order digital BBPLL with reference clock jitter. We derive the Chapman-Kolmogorov equation which statistically characterizes the timing jitter process. The numerical solution of this equation allows us to compute the timing jitter probability density function (PDF) in steadystate and to examine the effect of varying loop detuning and RMS reference clock jitter on the timing offset, the RMS timing jitter and the mean number of steps to slip a cycle. The analysis shows that the steady-state PDF is Gaussian-like only for a small range of RMS clock jitter values, which leads to a new curve for the BPD gain as a function of jitter.
517Scopus© Citations 6 - PublicationOutput-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitterBang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white phase noise) in second-order DBBPLLs, comparing the output jitter with that of first-order DBBPLLs. For small clock jitter, the nonlinear loop behavior is modeled as a two-dimensional Markov chain, and the output jitter is smaller than but close to that of a first order loop. For large clock jitter, the BPD nonlinearity is linearized, and the output jitter is larger than that of a first order loop; it is proportional to clock jitter and inversely proportional to the square root of the stability factor—the ratio of the proportional path gain to the integral-path gain of the digital loop filter.
1023Scopus© Citations 6 - PublicationCombined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loopsRecently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional charge-pump-based analog PLLs. This paper is concerned with a class of DPLLs employing a binary-quantized phase detector, referred to as bangbang PLLs (BBPLLs). They are widely used in clock and data recovery circuits and have recently been implemented as digital BBPLLs for high-bandwidth synthesis. Given that a DPLL implementation typically suffers from (excess) loop delay, this paper investigates the combined effect of loop delay and reference clock jitter in a first-order digital BBPLL. To statistically characterize the loop’s timing jitter we formulate it as a discrete-time vector Markov process and numerically solve the associated Chapman-Kolmogorov equation. This allows us to compute the timing jitter probability density function in steady-state and to evaluate the jitter performance (timing offset and RMS timing jitter) for varying loop detuning, RMS reference clock jitter and loop delay.
439Scopus© Citations 5