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Staszewski, Robert Bogdan
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Staszewski, Robert Bogdan
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Staszewski, Robert Bogdan
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Now showing 1 - 10 of 53
- PublicationA 60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoMA 60 GHz frequency generator with implicit ÷3 divider is proposed in this work to improve the system-level efficiency and phase noise. A third-harmonic boosting technique is utilized to simultaneously generate 20GHz and sufficiently strong 60 GHz signals in order to avoid any divider operating at 60 GHz. The prototype is fabricated in 40nm CMOS and exhibits a phase noise of −100 dBc/Hz at 1MHz offset from 60 GHz carrier and 25% tuning range. The phase noise and FoMT (figure-of-merit with tuning range) are improved by 5 dB and 4.6 dB, respectively, compared to state-of-the-art.
636Scopus© Citations 12 - PublicationCharge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM ReceiversRF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and RF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digitally intensive domain for a wireless RF transceiver, so that it enjoys benefits of digital and switched-capacitor approaches. Direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio. We further present details of the RF receiver front end for a GSM radio realized in a 90-nm digital CMOS technology. The circuit consisting of low-noise amplifier, transconductance amplifier, and switching mixer offers dB dynamic range with digitally configurable voltage gain of 40 dB down to dB. A series of decimation and discrete-time filtering follows the mixer and performs a highly linear second-order lowpass filtering to reject close-in interferers. The front-end gains can be configured with an automatic gain control to select an optimal setting to form a trade-off between noise figure and linearity and to compensate the process and temperature variations. Even under the digital switching activity, noise figure at the 40 dB maximum gain is 1.8 dB and dBm IIP2 at the 34 dB gain. The variation of the input matching versus multiple gains is less than 1 dB. The circuit in total occupies 3.1 . The LNA, TA, and mixer consume less than mA at a supply voltage of 1.4 V.
686Scopus© Citations 26 - PublicationBroadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM CompensationIn this paper, we present a design technique for broadband fully integrated GaN power amplifiers (PAs), with merged bandpass filter (BPF) and AM-PM compensation. The minimum-inductance BPF structure is used as the output matching network of the PA. A new theory of the minimum-inductance BPF is developed and it is shown that, compared to the standard BPF, it can be implemented using lower total inductance and provide higher out-of-band attenuation. Furthermore, using a two-transistor architecture, an AM-PM compensation technique is proposed where compressive and expansive nonlinearity profiles of the transistors' transconductance and gate-source capacitance are combined to achieve a linear total transconductance and input capacitance, over a wide power range. A fully integrated PA prototype, implemented in a 0.25- μm GaN-on-SiC process with 28-V supply, provides 35.1-38.9,dBm output power, 45-61% drain efficiency (DE), 40-55% power-added efficiency (PAE), and 11.3-13.4,dB power gain, across 2.0-4.0,GHz. For a 256-QAM signal with 7.2-dB PAPR and 100-MHz bandwidth at 2.4,GHz, it achieves 2.5% (-32.0,dB) rms error vector magnitude (EVMrms) and -37.5/-37.6,dBc adjacent channel leakage ratio (ACLR), while average output power and DE/PAE are respectively 30.1,dBm and 20.6/19.5%, without predistortion. EVMrms and ACLR can be improved to 0.5% (-46,dB) and -46.4/-46.8,dBc by using digital predistortion (DPD).
462Scopus© Citations 17 - PublicationOscillator-based ADCs: An exploration of time-mode analog-to-digital conversionThis paper introduces two novel ideas within the field of time-mode oscillator-based analog-to-digital conversion. In the form of a self-injection-locked ring-oscillator (SILRO), a method is presented to inherently linearise the voltage-to-frequency (V-F) characteristic, while an alternative proposal of an ultra-low-power (ULP), ultra-low-voltage (ULV) VCO-based analog-to-digital converter (ADC) operating in weak-inversion at a supply of 0.2 V is suitable for high power efficiency, direct energy harvesting applications. The ideas are distinctly separate in concept and physical implementation, but through the common platform of Verilog-A behavioural modelling, a unified methodology applicable to both architectures is proposed for system level exploration and performance evaluation.
703Scopus© Citations 1 - PublicationA Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS(Springer, 2006-06-27)
; ; ; ; We present a discrete-time second-order multibit sigma-delta ADC that filters and decimates by two the input data samples. At the same time it provides gain control function in its input sampling stage. A 4-tap FIR switched capacitor (SC) architecture was chosen for antialiasing filtering. The decimation-by-two function is realized using divided-by-two clock signals in the antialiasing filter. Antialiasing, gain control, and sampling functions are merged in the sampling network using SC techniques. This compact architecture allows operating the preceding blocks at twice the ADC's clock frequency, thus improving the noise performance of the wireless receiver channel and relaxing settling requirements of the analog building blocks. The presented approach has been validated and incorporated in a commercial single-chip Bluetooth radio realized in a 1.5 V 130 nm digital CMOS process. The measured antialiasing filtering shows better than 75 dB suppression at the folding frequency band edge. A 67 dB dynamic range was measured with a sampling frequency of 37.5MHz.306 - PublicationUnbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency EnhancementIn this article, we present a new broadband power amplifier (PA) architecture with a back-off efficiency enhancement that supports very wide modulation bandwidths. The unbalanced PA is composed of two cooperating sub-PAs using the Lange couplers as input power splitter and output power combiner. The PA operation is controlled by the transistors' width ratio and coupling coefficients of the Lange couplers. The output power back-off (OPBO) level is given by the transistors' width ratio and coupling coefficient of the output coupler, while the maximum efficiency is achieved at the back-off point. These features provide more design flexibility compared with the conventional Doherty PA, where the OPBO can be set only by the transistors' width ratio, and the maximum efficiency is achieved at the peak power. Using broadband harmonic matching networks, the main and auxiliary sub-PAs operate in the continuous mode to improve efficiency over a broad bandwidth. A fully integrated unbalanced PA, implemented in a 250-nm GaN-on-SiC process, achieves 32.2-34.3-dBm output power, 27%-37% efficiency at peak power, and 27%-40% at 5-6-dB back-off, across 4.5-6.5 GHz. The PA provides 3.7/4.5% (-28.6/-26.9 dB) rms error vector magnitude (EVMrms) and 30% average efficiency for a 256-QAM signal with 100-/200-MHz bandwidth, 7.2-dB PAPR, and 25.5-dBm average output power, without using any predistortion.
Scopus© Citations 15 673 - PublicationBroadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM-PM CompensationIn this paper, we present a design technique for broadband linearized fully integrated GaN power amplifiers (PAs). The minimum inductor bandpass filter structure is used as the output matching network to achieve low loss and high out-of-band attenuation. Two parallel transistors with unbalanced gate biases are used to mitigate nonlinearity of their transconductance and input capacitance, and consequently, compensate AM-PM distortion of the PA. A fully integrated GaN PA prototype provides 35.1–38.9 dBm output power and 40-55% power-added efficiency (PAE) in 2.0–4.0 GHz. For a 64-QAM signal with 8-dB peak-to-average power ratio (PAPR) and 100-MHz bandwidth at 2.4 GHz, average output power of 32.7 dBm and average PAE of 31% are measured with −30.2 dB error vector magnitude (EVM).
796Scopus© Citations 10 - PublicationDigital Deep-Submicron CMOS Frequency Synthesis for RF Wireless ApplicationsTraditional designs of commercial frequency synthesizers for multi-GHz mobile RF wireless applications have almost exclusively employed the use of a charge-pump phase-locked loop (PLL), which acts as a local oscillator (LO) for both transmitter and receiver. Unfortunately, the circuits and techniques required are extremely analog intensive and utilize a process technology which is incompatible with a digital baseband. The author's research related to low-power and low-cost radio solutions has led to a novel all-digital synthesizer architecture that exploits strong advantages of a deep-submicron digital CMOS process technology as well as advances in digital very large scale of integration (VLSI) field. Its underlying theme is to maximize digitally-intensive implementation by operating in a synchronous phase domain. Chief benefit obtained with this architecture is to allow to integrate the RF front-end with the digital back-end onto a single silicon die. The presented frequency synthesizer naturally combines the transmitter modulation capability implemented in an all-digital manner. The pulse-shaping transmit filter and a class-E power amplifier are included to demonstrate the use of the proposed synthesizer in a targeted RF application. The ideas developed in this research project have been implemented in a Texas Instruments' deep-submicron CMOS process and demonstrated in a working silicon of Bluetooth transmitter for short-range communications.
895 - PublicationA Class-F CMOS OscillatorAn oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases thus reducing the oscillator's effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency are achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators' structures shows the proposed class-F exhibits the lowest phase noise at the same tank's quality factor and supply voltage. The prototype of the class-F oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of -136 dBc/Hz at 3 MHz offset from the carrier over 5.9-7.6 GHz tuning range with figure-of-merit of 192 dBc/Hz. The oscillator occupies 0.12 mm2 while drawing 12 mA from 1.25 V supply.
339Scopus© Citations 178 - PublicationChallenges in On-Chip Antenna Design and Integration with RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems(Institute of Electrical and Electronics Engineers (IEEE), 2019-03-18)
; ; ; ; ; This paper investigates design considerations and challenges of integrating on-chip antennas in nanoscale CMOS technology at millimeter-wave (mm-wave) to achieve a compact front-end receiver for 5G communication systems. Solutions to overcome these challenges are offered and realized in digital 28-nm CMOS. A monolithic on-chip antenna is designed and optimized in the presence of rigorous metal density rules and other back-end-of-the-line (BEoL) challenges of the nanoscale technology. The proposed antenna structure further exploits ground metallization on a PCB board acting as a reflector to increase its radiation efficiency and power gain by 37.3% and 9.8 dB, respectively, while decreasing the silicon area up to 30% compared to the previous works. The antenna is directly matched to a two-stage low noise amplifier (LNA) in a synergetic way as to give rise to an active integrated antenna (AIA) in order to avoid additional matching or interconnect losses. The LNA is followed by a double-balanced folded Gilbert cell mixer, which produces a lower intermediate frequency (IF) such that no probing is required for measurements. The measured total gain of the AIA is 14 dBi. Its total core area is 0.83 mm2 while the total chip area, including the pad frame, is 1.55 \times 0.85 mm2.1261Scopus© Citations 41