Analytical Approach to Statistical Logic Cell Delay Analysis and its Extension to a Timing Graph

In this paper we propose a new methodology to determine the delay of combinational circuits within the framework of statistical static timing analysis (SSTA). The methodology is based on exact analytical solutions for the probability density functions of logic gate delays. Assuming initial delays of the input arrival times and operation time of gates to be normally distributed, the non-Gaussian distribution of the resulting delay of a gate is obtained, as well as its first two moments. This allowed us to propose a novel closed-loop algorithm for the calculation of delay propagation in combinational circuits. Possible extensions and future steps are discussed.