Hardware-in-the-Loop Validation of the Frequency Divider Formula

This paper validates a theoretical approach, namely, the frequency divider formula, recently proposed by the first and fourth authors to estimate local frequency variations based on the synchronous machine rotor speeds and on signals from phasor measurement units (PMUs). The validation is based on simulations performed in a Real-Time Digital Simulator with physical PMUs connected in the loop. The case study considers the well-known WSCC 3-machine, 9-bus test system. Simulation results show the high accuracy of the frequency divider formula to estimate the frequency at every bus of the network. Results also show that the frequency divider prevents the numerical issues due to fast variations of the voltage when measured by the PMU and indicate that such a formula can be utilized to test the fidelity of PMU implementations.