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FPGA Based Modelling of an ADPLL Network
Date Issued
2019-07-18
Date Available
2019-11-15T12:26:11Z
Abstract
This paper introduces and compares the implementation of a number of FPGA based ADPLL network prototyping architectures. Networks are then created using three different ADPLL implementations and tests performed on each. Based on these test results, comparison is made to both the expected performance and role of each ADPLL design as a development tool.
Type of Material
Conference Publication
Publisher
IEEE
Copyright (Published Version)
2019 IEEE
Web versions
Language
English
Status of Item
Peer reviewed
Journal
2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
Conference Details
The 2019 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, 15-18 July 2019
ISBN
978-1-7281-1201-5/19
This item is made available under a Creative Commons License
File(s)
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Name
smacd_fpga_adpll_paper.pdf
Size
243.78 KB
Format
Adobe PDF
Checksum (MD5)
58c609e2d29a3a7e524e6eb477364b89
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