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  5. Linearized discrete-time model of higher order charge-pump PLLs
 
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Linearized discrete-time model of higher order charge-pump PLLs

Author(s)
Bi, Chuang  
Curran, Paul F.  
Feely, Orla  
Uri
http://hdl.handle.net/10197/3595
Date Issued
2011-08-29
Date Available
2012-05-01T11:44:50Z
Abstract
In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs). The behaviour of CP-PLLs in the steady state is analysed
and an important feature is developed. The nonlinear state equations of CP-PLLs are linearized around the equilibrium point. The linearized discrete-time model is finally verified using behavioral simulations in Matlab and PSpice.
Sponsorship
Science Foundation Ireland
Type of Material
Conference Publication
Publisher
IEEE
Copyright (Published Version)
2011 IEEE
Subjects

Phase-locked loops

Charge-pump

Subject – LCSH
Phase-locked loops
On-chip charge pumps
DOI
10.1109/ECCTD.2011.6043385
Web versions
http://dx.doi.org/10.1109/ECCTD.2011.6043385
Language
English
Status of Item
Peer reviewed
Journal
2011 20th European Conference on Circuit Theory and Design (ECCTD) [proceedings]
Conference Details
European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, 29-31 August, 2011
ISBN
978-1-4577-0617-2
This item is made available under a Creative Commons License
https://creativecommons.org/licenses/by-nc-sa/1.0/
File(s)
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ECCTD11_Chuang.pdf

Size

94.04 KB

Format

Adobe PDF

Checksum (MD5)

8f4c3c5ebc4f2bd9a323f3e676195961

Owning collection
Electrical and Electronic Engineering Research Collection

Item descriptive metadata is released under a CC-0 (public domain) license: https://creativecommons.org/public-domain/cc0/.
All other content is subject to copyright.

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