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  5. A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS
 
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A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS

File(s)
FileDescriptionSizeFormat
Download 2015-01-26_vlsi_madadi_dtrx.pdf1.35 MB
Author(s)
Madadi, Iman 
Tohidian, Massoud 
Cornelissens, Koen 
Vandenameele, Patrick 
Staszewski, Robert Bogdan 
Uri
http://hdl.handle.net/10197/7301
Date Issued
19 June 2015
Date Available
14T13:27:23Z December 2015
Abstract
A SAW-less discrete-time superheterodyne receiver (RX) with multi-stage harmonic rejection in 28nm CMOS, featuring highly linear LNTA, employs a novel blocker-resilient octal charge-sharing band-pass filter to achieve low power consumption. The RX features NF of 2.1 to 2.6dB, and IIP3 of 8 to 14 dBm, while drawing only 24 to 37 mW in different operation modes.
Other Sponsorship
M4S/Hisilicon, Leuven, Belgium
Type of Material
Conference Publication
Publisher
IEEE
Copyright (Published Version)
2015 IEEE
Keywords
  • Superheterodyne recei...

  • Power consumption

DOI
10.1109/VLSIC.2015.7231302
Language
English
Status of Item
Peer reviewed
Part of
Proceedings of IEEE Symposium on VLSI Circuits (VLSI), Kyoto, Japan 2015
Description
IEEE 2015 Symposium on VLSI Circuits (VLSI), Kyoto, Japan, 17 -19 June 2015
This item is made available under a Creative Commons License
https://creativecommons.org/licenses/by-nc-nd/3.0/ie/
Owning collection
Electrical and Electronic Engineering Research Collection
Scopus© citations
7
Acquisition Date
Jan 25, 2023
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Views
1565
Acquisition Date
Jan 26, 2023
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Downloads
399
Last Week
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Acquisition Date
Jan 26, 2023
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