Ultra-Low-Power Phase-Tracking Receivers for IoT Applications

The worldwide market of Internet-of-Things (IoT) is growing at a fast exponential rate due to the confluence of several driving forces: the explosion of end-user devices, demand for ubiquitous connectivity, and the continual evolution of available technologies. To keep up with this exponential growth, system portability and energy autonomy of the connected IoT devices are paramount. This indicates that the IoT nodes must be powered up through an inexpensive coin battery or directly from an energy harvesting (EH) source. Although EH is promising, the range of supported IoT applications is restricted due to the limited energy availability and excessive system power dissipation. Therefore, powering the IoT node via batteries is so far the most robust and efficient solution. To improve the battery longevity, ultra-low-power (ULP) and ultra-low-voltage (ULV) design approaches both become increasingly significant. Among the major blocks of an IoT node is a wireless receiver (RX). Although much effort has been made to optimize the power efficiency for constituent sub-blocks of the RX, it becomes more challenging to further reduce its power allocation, where some key RF blocks [i.e., low-noise amplifier (LNA) and local oscillator (LO)] dominate most of the power budget to satisfy the stringent sensitivity and linearity requirements. Besides, in the nanometer-scale CMOS territory, the low intrinsic gain and high threshold voltage further limit the room for circuit-level innovation. In this dissertation, we focus on improving power efficiency mainly from an architectural perspective. A first-ever type-II phase-tracking (PT)-RX architecture is proposed with the record best-in-class power efficiency. By employing a multibit analog-to-digital converter (ADC), the proposed PT-RX zeros out its automatic frequency calibration (AFC) offset, which is a severe issue in the prior type-I PT-RXs. Because of the removed AFC offset, the type-IIloop is also very tolerant for long run-lengths of consecutive “1” or “0” symbol sequences. Besides, the ADC, along with a passive mixer, functions as a multi-level phase detector (PD) with an enlarged linear range of small-signal gain, which ensures unconditionally stable locking in the steady-state. This prototype of PT-RX targets Bluetooth low energy (BLE) standard, consuming only 1.5 mW at a supply of ≤0.7V and is fabricated in a mainstream 28-nm LP CMOS process technology from TSMC. It maintains a cutting-edge performance of in-band interference and out-band blocker rejection while also offering the best-in-class figure-of-merit (FoM) of 181 dB (when it was firstly reported), with a 1 Mbps BLE sensitivity of −93 dBm. Moreover, to further validate the innate advantages of the type-II architecture in terms of power efficiency, we present our second version of PT-RX achieving the sensitivity of −93.2dBm with merely 0.9mW power consumption. To the best of our knowledge, the proposed receiver achieves the best sensitivity FoM of 183.2 dB among the BLE receivers. It also addresses the commonly found pulling issue in the zero-IF PT-RXs, which in our case happens through magnetic coupling from the on-chip inductor of a low-noise trans- conductance amplifier (LNTA) into a digitally controlled oscillator (DCO). This is solved by employing an inductor-free structure of LNTA. As a result, a 1.5—2.5-dB improvement of the adjacent channel rejection (ACR) is obtained. Lastly, as part of the future research suggestions, a non-linear waveform-tracking filter is proposed to overcome the constraint between loop delay and interference rejection in the PT- RXs. It promises a 1–2-dB improvement of ACR per simulation. Preliminary measurement results are given.