Contributions to the theory and development of low-jitter bang-bang integrated frequency synthesizers

The advent of next-generation wireless standards demands ever-increasing data-rate communication systems. It mainly involves a higher carrier frequency to take advantage of wider bandwidth channels and more complex modulation schemes to pack more information into each symbol. In this context, the bottleneck is represented by the frequency synthesizer used to generate the local oscillator signal for the transceiver, which has to operate under stringent low output jitter requirements. Such performance must be provided at low power dissipation and area consumption in order to meet the requirements of low-cost and high integration level of the modern communication systems. The digital phase locked loop architecture can meet the required jitter performance while synthesizing fractional-N frequencies. Such PLLs offer significant advantages over their traditional analog counterpart in terms of area occupation, flexibility and scalability in advanced deep sub-µm CMOS technologies. The digital PLL topology based on a bang-bang phase detector, denoted bang-bang PLL, which is a single bit digital phase detector, leads to a less complex and more power-efficient architecture, but, on the other hand, it also introduces a hard nonlinearity in the loop, making the analysis of the bang-bang topology more challenging than in the multi-bit case. A comprehensive phase noise analysis of bang-bang digital PLLs is presented which overcomes the limitations of previous models and it is valid in all cases where physical noise sources (i.e. reference and DCO) are dominant with respect to quantization errors. In particular, (i) input-referred jitter is estimated by means of a linear time-domain analysis derived from a nonlinear DPLL model, and (ii) phase noise spectra are predicted using a discrete-time domain model that accounts for time-variant effects that arise from the intrinsic multirate nature of the DPLL. The possibility of accurately determining the DPLL jitter and phase noise spectra, enabled by the novel analysis presented in this thesis, is key to significantly speeding up the design-space exploration phase, since it allows one to perform quick and precise parametric sweeps. However, even when designed properly, bang-bang PLLs are affected by the unavoidable bang-bang phase detector quantization noise, which is added on top of the intrinsic reference and DCO phase noise. The quantization noise can be appreciated in the PLL's output spectrum as increased in band noise with respect to the analog counterpart, that, in fact, still achieves superior performance in terms of jitter-power. This results in worse integrated jitter performance for the same intrinsic levels of reference and oscillator phase noise. To overcome the binary phase detector quantization noise in DPLLs, state-of-the-art works rely on a multi-bit time-to-digital converter to digitize the PLL phase error with a physical resolution below the input jitter, leading to increased design complexity, with an associated area and power penalty. In order to overcome the ultimate limit of the bang-bang PLL, a digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping has been fabricated in a 28nm CMOS process. The prototype occupies a core area of 0.21 mm2 and draws 10.8 mW power from a 0.9 V supply. The integrated jitter is 69.52 fs and 80.72 fs for the integer-N and the fractional-N case, respectively. Achieving a jitter-power figure-of-merit of -251.5 dB in fractional-N mode, the proposed system effectively bridges the gap to analog implementations. The first chapter of this work is introductory, and is intended to give some background information needed to underpin the remaining part of the thesis. The following chapters, 2, 3 and 4, collect the results achieved during the PhD activity, and each of them is associated with a publication. In the last chapter, conclusions are drawn and the open points are discussed in order to be considered for future work.