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  5. Dynamic Current Modelling at the Instruction Level
 
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Dynamic Current Modelling at the Instruction Level

Author(s)
Rizo-Morente, J.  
Casas-Sanchez, M.  
Bleakley, Chris J.  
Uri
http://hdl.handle.net/10197/7060
Date Issued
2006-10-06
Date Available
2015-09-17T15:34:37Z
Abstract
Estimation of processor current consumption is important for the design of low power systems. This paper proposes a novel method for estimating the dynamic current consumption of a processor. The method models dynamic current as the output of a linear system excited by a signal comprised of the total current due to each instruction. System identification is performed by cross-correlation of a pseudo-random stimulus with the measured current. The method was applied to the Texas Instruments TMS320VC5510 DSP and was found to provide an average correlation of 93% between estimated and measured dynamic current across a range of benchmarks.
Type of Material
Conference Publication
Publisher
IEEE
Copyright (Published Version)
2006 ACM
Subjects

Measurements

Experimentation

Design

Verification

DOI
10.1109/LPE.2006.4271814
Language
English
Status of Item
Peer reviewed
Conference Details
International Symposium on Low Power Electronics and Design (ISLPED), Tegernsee, Germany, 4 - 6 October, 2006
This item is made available under a Creative Commons License
https://creativecommons.org/licenses/by-nc-nd/3.0/ie/
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Dynamic_Current_Modeling_at_the_Instruction_Level.pdf

Size

314.14 KB

Format

Adobe PDF

Checksum (MD5)

1c13d940bbc7d363f5503ace0af7e66b

Owning collection
Computer Science Research Collection

Item descriptive metadata is released under a CC-0 (public domain) license: https://creativecommons.org/public-domain/cc0/.
All other content is subject to copyright.

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