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Area-Delay Efficient Arithmetic Mixed-Radix Conversion for Fermat Moduli
Date Issued
2011-07-10
Date Available
2015-10-14T09:24:07Z
Abstract
Mixed Radix Conversion is an essential feature of error detection and correction in Redundant Residue Number Systems. Fermat numbers are a popular choice as moduli in these systems. However, Fermat numbers are typically implemented using Diminished–1 arithmetic which necessitates special consideration of zero in arithmetic operations. Furthermore, the sequential nature of Mixed Radix Conversion leaves it prone to considerable delay due to carry propagation in adders at each stage. In this paper, Diminished-1 arithmetic in carry save form is used to give significant reductions in area and delay compared to previously proposed hardware architectures. The percentage area reduction was found to range from 13% to 41% and that of delay from 19% to 49% for bit widths from 8 to 28 bits.
Type of Material
Journal Article
Publisher
The Institute of Electronics, Information and Communication Engineers
Journal
IEICE Electronics Express
Volume
8
Issue
13
Start Page
1040
End Page
1046
Copyright (Published Version)
2011 IEICE
Language
English
Status of Item
Peer reviewed
This item is made available under a Creative Commons License
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Name
Area-Delay_Efficient_Arithmetic_Mixed-Radix_Conversion_for_Fermat_Moduli.pdf
Size
103.76 KB
Format
Adobe PDF
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