Ultra-Low Jitter and Energy-Efficient Frequency Synthesis for mmWave Communications

Modern wireline and wireless communication systems, which employ complex modulation schemes, require highly precise clock generation with stringent specifications for phase noise and jitter while minimizing spurious tones. These requirements become even more challenging under the strict low-power constraints of handheld devices and Internet-of-Things (IoT) applications. One approach to addressing these challenges is to use low-power oscillators with moderate phase noise performance while leveraging phase-locked loop (PLL) architectural innovations to achieve a larger bandwidth. Injection-locked type of frequency synthesizers, such as charge-sharing locking (CSL) PLLs, can meet these specifications without compromising PLL stability. However, they tend to generate large reference spurs due to periodic load modulation of the LC-tank. To mitigate this issue while enhancing power efficiency, this thesis proposes a novel ping-pong (PP) CSL PLL architecture. The PP CSL PLL strengthens charge injection into the oscillator’s LC-tank by utilizing complementary charge-sharing capacitors during both the positive and negative halves of the reference clock, effectively achieving an implicit 2× reference frequency multiplication. Implemented in 28nm CMOS, the proposed PP-CSL PLL operates at approximately 27 GHz with the aid of a class-F3 oscillator and a third-harmonic extractor. This design demonstrates a threefold increase in injection strength compared to conventional CSL PLLs while mitigating load modulation issues, leading to an approximately 15dB improvement in reference spur suppression. It achieves an ultra-low RMS jitter of 42 fs with a power consumption of only 14 mW, resulting in an exceptional jitter-normalized figure of merit (FoMjitter−N) of −276.6 dB. To further enhance clock generation efficiency, this work presents a digitally controlled oscillator (DCO) that operates from 13.8 to 16.2 GHz while consuming only 580-μW, the most power-efficient oscillator reported in this frequency range. Fabricated in 28 nm CMOS, the DCO achieves a phase noise of -121 dBc/Hz at a 10 MHz offset from a 14 GHz carrier, corresponding to an FoM of -188 dBc/Hz. When integrated with the proposed PP-CSL architecture, this DCO enables at least a 5 dB improvement in the overall PLL figure of merit, highlighting the synergy between low-power oscillator design and architectural innovation. Finally, the thesis explores oscillator architectures suitable for both emerging and infrastructure-grade wireless systems. A rotary traveling wave oscillator (RTWO) is presented that achieves the best figure-of-merit among reported RTWOs, substantially closing the performance gap with conventional LC-tank designs and establishing RTWOs as a practical candidate for multi-phase injection locking for high-bandwidth applications and efficient sub-THz generation. Additionally, a compact series-resonance oscillator (SRO), leveraging a tri-filar transformer, is developed for base station applications. This SRO achieves a >20% tuning range around ∼11 GHz while consuming only 55 mW, and delivers phase noise of -125 dBc/Hz at a 1 MHz frequency offset, thereby offering a compelling alternative to large-area multi-core oscillator solutions in high-performance systems.