Edge-Combining Switched-Capacitor mm-Wave Digital-to-Analog Converter

The fifth generation (5G) of cellular network technology has enormous potential to revolutionize society by reshaping both our personal and professional lives. 5G technology will enable applications such as high-definition entertainment streaming, virtual/augmented reality environments, providing better healthcare ecosystems to autonomous transport. Central to this vision is the development of the 5G network infrastructure, such as transceiver hardware systems with orders-of-magnitude performance improvement compared to the fourth generation (4G) devices in terms of bandwidth, latency, power efficiency and network capacity. The 5G transmitter represents a crucial transceiver sub-system and is particularly challenging to design due to the strict requirements on power consumption. Consisting primarily of a high-speed digital-to-analog converter (DAC), mixer and power-amplifier (PA), these analog blocks consume a significant portion of the overall transceiver power budget. Moreover, the design specifications of the transmitter is heavily coupled to the development of complementary metal-oxide-semiconductor (CMOS) technology. With the migration to deeply scaled CMOS, the transistor length is reduced to as small as 5\,nm (i.e., in a FinFET process). Unfortunately, the analog-intensive nature of a conventional transmitter design makes it extremely difficult to scale with the technology (unlike with digital logic gates), resulting in degraded output power, power efficiency and transistor reliability. These issues are further compounded with transmitter implementations for the upper-band 5G mmW frequency range between 26--28\,GHz and 37--39\,GHz, for Europe and Asia, respectively. In this scenario, the introduction of the \emph{digital-RF paradigm} represents a promising approach to overcome the aforementioned inherent limitations of conventional analog-transmitters. The digital-RF approach brings the digital circuitry up to the traditionally analog-dominated RF-domain and thereby enables an all-digital, all-in-one architecture embedding the DAC, mixer and PA functions within a radio-frequency digital-to-analog converter (RFDAC) transmitter. While significant efforts in both industry and academia have produced power-efficient, high-resolution RFDACs, their current operation is limited to only the lower-band 5G standards (i.e., sub-6\,GHz frequency band), owing to the need to perform \emph{hard-switching} of the RFDAC power devices. In this dissertation, we develop an RFDAC architecture which can operate in the mmW frequency regime (thereby we coin the term `mmW-DAC'), with the intention of advancing the digital-RF towards the \emph{digital-mmW} paradigm. The introduction of the \emph{edge-combining} techniques enables the power-generating devices within the RFDAC output stage to switch at sub-harmonic frequencies, relaxing the transition time specifications of digital transition edges. The edge-combining RFDAC (EC-RFDAC) unit cells are inspired by the operation of a digital XOR gate, allowing an implicit multiplication of the effective clock carrier frequency at the output stage. Applying these techniques in the mmW frequency band results in an \emph{increased energy efficiency} without any loss to the output power. Therefore, the implementation of the edge-combining RFDAC overcomes the speed limitations associated with the transit frequency ($f_T$) limit of the transistor for a given CMOS technology.