Ultra-Low-Voltage VCO-Based ADCs

The Internet-of-Things (IoT) paradigm continues to drive the research and development of energy-harvesting (EH) wireless sensor network (WSN) nodes. The operation of ‘smart’ IoT devices that are always on and always sensing offers intelligent interactivity and communication with their dynamic environment. Such technology innovations enable IoT applications ranging from smart agriculture, industrial automation to personal health monitoring and home connectivity solutions. Paramount to this vision is the design of ultra-low-voltage (< 0.3V) and ultra-low-power (µW-level) WSN building blocks. An analog-to-digital converter (ADC) represents a critical WSN sub-system. Its role is to digitize voltage/current signals for a downstream digital signal processor to process and interpret meaning from the inherently analog world we live in. However, the functionality of an ultra-low-voltage ADC is particularly difficult to realize, even in advanced nanometer complementary metal oxide-semiconductor (CMOS) technology. Conventional voltage-domain analog signal processing techniques rely heavily on analog-intensive operational-amplifiers (op-amps) and current sources, which do not scale well with the shrinking supply voltage and the CMOS process feature size. The voltage-controlled-oscillator (VCO)-based ADC topology offers an attractive solution that leverages time-domain signal processing techniques for digitally intensive, scaling-friendly and power-efficient data conversion. Despite recent architectural advancements of the VCO-based ADC and, consequently, its achievable performance for high resolution, high-bandwidth signal digitization, the ultra-low-voltage (ULV) design landscape, to date, remains an uncharted territory. The availability of a VCO-based ADC that can operate from a supply voltage as low as 0.2 V, will be able to support a wide range of sustainable energy sources (e.g., solar, vibration and heat harvesters) in WSNs and, therefore, lead to practical, portable and energy-autonomous EH IoT applications. The expositions in this dissertation explore ULV VCO-based ADC architectures which can be powered reliably with a single supply voltage of merely 0.2 V. The design and implementation of open-loop VCO-based ADCs in 28nm CMOS achieves resolution ranging from 10–11 bits, 50–200 kHz bandwidth (BW) and sampling rates up to 40 MS/s. By dissipating significantly less than 20 µW of power while exhibiting robustness across process-voltage-temperature (PVT) variations, coupled requirements for both power efficiency and PVT tolerance are resolved. Such results are supported by extensive experimental verification, demonstrating unprecedented performance for ULV operation that rival state-of-the-art VCO-based ADC designs typically requiring a supply voltage around 1 V. The development of these high-performance ‘mostly-digital’ ULV architectures incorporate several innovative circuit- and system-level design techniques. Variation-aware VCO analog linearization employs open-loop harmonic-distortion (HD) cancellation schemes with embedded PVT-sensing replica-VCO structures. A digitally re-configurable input interface accommodates diverse dynamic range requirements of multiplexed sensor arrays. Analog phase-domain signal processing (APSP) circuits performing beat-frequency extraction, phase-interpolation, phase-averaging and phase-folding bring new dimensions of flexibility and power-efficiency to the design of ULV VCO-based ADCs. Precise frequency digitization is enabled through a high-speed phase-sampling interface, easily extended from single-bit to multi-bit (i.e., multiphase) configurations. Hardware redundancy techniques achieve fault-tolerant operation, while speed bottlenecks in the synchronous digital processing back-end are overcome with the construction of polyphase, multi-rate digital hardware.