Hardware-in-the-Loop Validation of the Frequency Divider Formula

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Title: Hardware-in-the-Loop Validation of the Frequency Divider Formula
Authors: Ortega, Alvaro
Musa, Aysar
Monti, Antonello
Milano, Federico
Permanent link: http://hdl.handle.net/10197/10023
Date: 24-Dec-2018
Online since: 2019-04-18T07:34:14Z
Abstract: This paper validates a theoretical approach, namely, the frequency divider formula, recently proposed by the first and fourth authors to estimate local frequency variations based on the synchronous machine rotor speeds and on signals from phasor measurement units (PMUs). The validation is based on simulations performed in a Real-Time Digital Simulator with physical PMUs connected in the loop. The case study considers the well-known WSCC 3-machine, 9-bus test system. Simulation results show the high accuracy of the frequency divider formula to estimate the frequency at every bus of the network. Results also show that the frequency divider prevents the numerical issues due to fast variations of the voltage when measured by the PMU and indicate that such a formula can be utilized to test the fidelity of PMU implementations.
Funding Details: European Commission Horizon 2020
Science Foundation Ireland
Type of material: Conference Publication
Publisher: IEEE
Copyright (published version): 2018 IEEE
Keywords: Frequency estimationPhasor measurement unitsRotorsFrequency conversionFrequency synchronizationPhase locked loops
Other versions: https://www.ieee-ras.org/
Language: en
Status of Item: Not peer reviewed
Is part of: 2018 IEEE Power & Energy Society General Meeting (PESGM)
Conference Details: RCAR 2018 - IEEE International Conference on Real-time Computing and Robotics, Kandima, Maldives 1-5 August
Appears in Collections:Electrical and Electronic Engineering Research Collection

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