A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS
|Title:||A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS||Authors:||Chen, Peng; Zhang, Feifei; Zong, Zhirui; Zheng, Has; Siriburanon, Teerachot; Staszewski, Robert Bogdan||Permanent link:||http://hdl.handle.net/10197/11036||Date:||26-Dec-2017||Online since:||2019-08-26T13:40:12Z||Abstract:||This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.||Funding Details:||European Commission - Seventh Framework Programme (FP7)
Science Foundation Ireland
|Type of material:||Conference Publication||Publisher:||IEEE||Volume:||2017-January||Start page:||93||End page:||96||Copyright (published version):||2017 IEEE||Keywords:||Digital-to-time converter (DTC); Low-power; Low voltage; Power-efficient; Capacitor-based DAC (C-DAC); Constant slope; High resolution; INL; PLL||DOI:||10.1109/ASSCC.2017.8240224||Other versions:||http://www.asscc.org/2017/||Language:||en||Status of Item:||Not peer reviewed||Is part of:||2017 IEEE Asian Solid-State Circuits Conference (A-SSCC) - Proceedings of Technical Papers||Conference Details:||2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Grand Hilton Hotel, Seoul, Korea, 6-8 November 2017||ISBN:||9781538631782|
|Appears in Collections:||Electrical and Electronic Engineering Research Collection|
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