Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology

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Title: Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology
Authors: Galayko, DimitriShan, ChuanZianbetov, EldarBlokhina, Elenaet al.
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Date: 30-Jul-2019
Online since: 2019-11-15T10:12:49Z
Abstract: This brief presents an active distributed clock generator for manycore systems-on-chip consisting of a 10×10 network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequency range of 700–840 MHz at VDD=1.1 V. The network is highly robust against VDD variations. An energy cost of 2.7 μW /MHz per node is 7 times lower than that in analog implementations of similar architectures and is twice lower than that in conventional H-tree architectures. This is the largest on-chip all-digital phase-locked loop network ever implemented. With clock generation nodes linked only locally, this solution is proven to be scalable. The presented clock generation network does not require any external reference, except for the start-up frequency selection, generating a synchronized signal in fully autonomous mode and maintaining frequency stability within 0.09% during 1700 seconds. Such a network of frequency and phase synchronized oscillators can be used as a source for local clocking areas.
Funding Details: Enterprise Ireland
metadata.dc.description.othersponsorship: French National Agency of Research (ANR)
Type of material: Journal Article
Publisher: IEEE
Journal: IEEE Transactions on Circuits and Systems II: Express Briefs
Volume: 66
Issue: 10
Start page: 1673
End page: 1677
Copyright (published version): 2019 IEEE
Keywords: Phase frequency detectorClocksOscillatorsSynchronizationPhase locked loopsDetectorsFrequency synchronization
DOI: 10.1109/tcsii.2019.2932029
Language: en
Status of Item: Peer reviewed
Appears in Collections:Electrical and Electronic Engineering Research Collection

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