FPGA Based Modelling of an ADPLL Network

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Title: FPGA Based Modelling of an ADPLL Network
Authors: Dooley, C.Blokhina, ElenaMulkeen, BrianGalayko, Dimitri
Permanent link: http://hdl.handle.net/10197/11204
Date: 18-Jul-2019
Online since: 2019-11-15T12:26:11Z
Abstract: This paper introduces and compares the implementation of a number of FPGA based ADPLL network prototyping architectures. Networks are then created using three different ADPLL implementations and tests performed on each. Based on these test results, comparison is made to both the expected performance and role of each ADPLL design as a development tool.
Type of material: Conference Publication
Publisher: IEEE
Copyright (published version): 2019 IEEE
Keywords: Digital phase locked loopsField programmable gate arrays
DOI: 10.1109/smacd.2019.8795299
Other versions: https://www.smacd2019.com/
Language: en
Status of Item: Peer reviewed
Is part of: 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
Conference Details: The 2019 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, 15-18 July 2019
ISBN: 978-1-7281-1201-5/19
Appears in Collections:Electrical and Electronic Engineering Research Collection

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