Sampling Rate Reduction for Digital Predistortion of Broadband RF Power Amplifiers
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|Title:||Sampling Rate Reduction for Digital Predistortion of Broadband RF Power Amplifiers||Authors:||Li, Yue; Wang, Xiaoyu; Zhu, Anding||Permanent link:||http://hdl.handle.net/10197/11359||Date:||Mar-2020||Online since:||2020-04-30T14:36:54Z||Abstract:||In this article, we present a novel technique to build digital predistorters that can linearize broadband power amplifiers (PAs) using reduced sampling rates. In contrast to conventional digital predistortion (DPD) where oversampling is necessary to avoid aliasing effect, the proposed method cancels the aliasing distortion using a sliced multistage cancellation scheme. A large reduction of sampling rate can be achieved in digital implementation of DPD, significantly reducing power consumption and implementation cost. Experimental results show that a DPD with a sampling rate of merely 1.5x, instead of 5x, signal bandwidth, can still produce satisfactory performance within the linearization bandwidth but consume only one-third of power, compared with that using the conventional approaches. The proposed technique provides a promising solution for the next-generation 5G systems, where large signal bandwidths are required.||Funding Details:||Science Foundation Ireland||Type of material:||Journal Article||Publisher:||IEEE||Journal:||IEEE Transactions on Microwave Theory and Techniques||Volume:||68||Issue:||3||Start page:||1054||End page:||1064||Copyright (published version):||2019 IEEE||Keywords:||Bandwidth; Nonlinear distortion; Power demand; Predistortion; Broadband communication; Clocks||DOI:||10.1109/tmtt.2019.2944813||Language:||en||Status of Item:||Peer reviewed|
|Appears in Collections:||Electrical and Electronic Engineering Research Collection|
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