Low-Power Analog-to-Digital Converters in Nanometer CMOS for IoT Applications
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|Title:||Low-Power Analog-to-Digital Converters in Nanometer CMOS for IoT Applications||Authors:||Wang, Hongying||Permanent link:||http://hdl.handle.net/10197/11615||Date:||26-Mar-2020||Online since:||2020-10-02T16:00:52Z||Abstract:||The ever increasing demands for Internet-of-Things (IoT) networks promote the trend of power-efficient system design at the analog front-end, analog-to-digital converter (ADC), RF transmitter (TX) and digital signal processing (DSP) levels. This is further motivated by the relatively slow development in power storage technology and consumer expectations of long operational and stand-by times. To achieve inexpensive large-scale integration while exploiting improved digital power efficiency, IoT networks are preferably realized in a deep nanoscale CMOS technology. However, it is rather challenging and power-consuming to implement high-performance continuous-time (CT) amplifiers and comparators, which generally are indispensable elements for most conventional ADCs in deep nanometer CMOS given the low intrinsic gain of transistors and reduced supply voltage; therefore, passive and digitally intensive ADC topologies are attractive alternatives in deep nanometer CMOS to improve power efficiency. For applications demanding high resolution and good linearity, Delta-Sigma ADCs can be a suitable option since they can relax front-end anti-aliasing filtering and suppress in-band quantization noise by oversampling and noise-shaping techniques. To promote low power, passive integrators containing only switches and capacitors can be adopted. In this thesis, we demonstrate a passive switched-capacitor (sw-cap) modulator based on pipelined charge-sharing rotation in 28 nm CMOS, which not only eliminates any inter-stage loading effects that plague the conventional sw-cap passive modulators, but also relaxes settling requirements and improves power efficiency. For applications dealing with sparse signals and demanding low-medium resolution and compressed output data size, level-crossing (LC) ADCs can be a good option since they can produce an input-dependent average sampling rate, thus reducing the power consumption of the RF TX and DSP for data transmission and processing, respectively. In this thesis, we introduce a digitally intensive event-driven quasi-level-crossing (quasi-LC) delta-modulator ADC with an adaptive-resolution (AR) algorithm. The proposed AR quasi-LC delta modulator quantizes the residue voltage signal with a residue quantizer, which enables a straightforward implementation of LC and AR algorithms in the digital domain. The proposed modulator achieves data compression by means of a globally signal-dependent average sampling rate and achieves adaptive resolution through a digital multi-level comparison window which overcomes the trade-off between the dynamic range (DR) and input bandwidth as presented in conventional LC ADCs. The residue quantizer is firstly implemented as a Successive-Approximation-Register (SAR) sub-ADC for better power efficiency, and then it is also implemented as a voltage-controlled-oscillator (VCO)-based sub-ADC to achieve higher DR and average sampling rate for low-amplitude and slowly-varying signals.||Type of material:||Doctoral Thesis||Publisher:||University College Dublin. School of Electrical and Electronic Engineering||Qualification Name:||Ph.D.||Copyright (published version):||2020 the Author||Keywords:||Analog-to-digital converter (ADC); Delta-sigma; Inter-stage loading effect; Passive; Pipelining; Switched capacitor; Adaptive resolution (AR); Event-based signal processing; Asynchronous SAR ADC; Compressed sensing; Internet-of-Things (IoT); Level-crossing (LC)||Language:||en||Status of Item:||Peer reviewed|
|Appears in Collections:||Electrical and Electronic Engineering Theses|
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