Time domain converters and ultra-low-power all-digital phase-locked-loop

Files in This Item:
Access to this item has been restricted by the copyright holder until:2021-11-01
File Description SizeFormat 
PhD_Thesis_PengCHEN.pdf4.61 MBAdobe PDF    Request a copy
Title: Time domain converters and ultra-low-power all-digital phase-locked-loop
Authors: Chen, Peng
Permanent link: http://hdl.handle.net/10197/12136
Date: 2019
Online since: 2021-04-30T15:29:40Z
Abstract: Internet-of-Things promise the devices the ability to connect, collect and exchange data with little or no human-to-human or human-to-computer intervention. The continued demand for low cost and low power of wireless communications drive research that explores new architectures and techniques in the RF front-end. Time-domain operations are favored by the technology scaling, thanks to the steeper and steeper transition edges having the ability to carry information. Two fundamental time-domain data converters are time-to-digital converter (TDC) and digital-to-time converter (DTC). First, a novel discharging constant-slope DTC is proposed, consuming merely 31 μW running at 40 MHz. Taking advantage of the constant-slope operation, it achieves 1.07 LSB in a 9-bit implementation with a typical resolution of 148 fs. This work also uncovers for the first time two effects that are compensating each other: channel length modulation is compensated by the ramp node varactor. Compared with other constant-slope DTC counterparts and other DTC architectures, the proposed work achieves an outstanding performance. Then, the other basic time-domain block, time-to-digital converter, is introduced thoroughly in the introduction chapter with popular TDC architectures investigated and summarized. The proposed TDC work targets built-in-self-test applications. With the help of the proposed system self-calibration method, the non-ideal effects of analog blocks can be calibrated in a digital manner. The system achieves pico-second level precision with a low-quality clock available in the SoC environment. Two all-digital phase-locked-loops are designed with different applications and techniques. The first one utilizes a ΣΔ technique to dither the DTC control codes to suppress fractional spurs. In the mm-wave applications, it achieves around -30 dBc fractional spur at 60 GHz output. With the help of low noise contribution from the DTC and narrow TDC range benefited from Vernier architecture, the PLL achieves 213{277 fs RMS jitter in 57.5{67.2 GHz tuning range while consuming only 40mW. The second one is applied in the Bluetooth low energy applications. It pursues low power consumption for the PLL so that the battery life can be extended for the radios. With the help of the improved constant-slope DTC and hybrid TDC, together with an optimized low power inverse-class- F VCO, the PLL achieves sub-half-mW power consumption with 1 ps RMS jitter.
Type of material: Doctoral Thesis
Qualification Name: Ph.D.
Keywords: Digital-to-time converters (DTC)Time-to-digital converters (TDC)Low power wireless communications
Language: en
Status of Item: Peer reviewed
This item is made available under a Creative Commons License: https://creativecommons.org/licenses/by-nc-nd/3.0/ie/
Appears in Collections:Electrical and Electronic Engineering Theses

Show full item record

Page view(s)

checked on May 13, 2021


checked on May 13, 2021

Google ScholarTM


If you are a publisher or author and have copyright concerns for any item, please email research.repository@ucd.ie and the item will be withdrawn immediately. The author or person responsible for depositing the article will be contacted within one business day.