A Circuit Design Journey from Room Temperature to Cryo Temperature

The continual advancement of CMOS technology results in faster and more power efficient digital processing. Concurrently, the supply voltage of CMOS circuits is scaled lower and this leads to smaller voltage headroom, which raises challenges in designing analog circuits with every new CMOS technology node. To overcome these challenges, there have been significant interests in time-based analog-todigital converters (ADCs). To convert an input voltage signal to time domain, some kind of voltage-to-time conversion (VTC) is needed. The linearity of this VTC usually limits the performance of time-based ADCs. To solve these problems, this thesis proposes and realizes in TSMC 28-nm CMOS two new techniques in the time-based ADCs using a VTC. In the first design, the proposed ultra-low-voltage ADC makes use of a Dickson charge pump circuit (Dickson CP) as part of VTC to convert the input analog voltage into time domain by modulating the slope of the ramp. In the second design, to compensate the nonlinearity in the generated ramp signal from the Dickson CP, a digital compensation scheme is proposed. As the Moore’s law of scaling of transistors is losing its momentum, there have been significant interests aiming to extend the exponential growth in computing power by means of “quantum computing", which promises to solve sophisticated and currently intractable problems in various applications, such as simulation of chemical reactions, modeling financial transactions, finding cure for COVID-19, etc. In order to control the extremely fragile quantum bits (qubits) with an accurate manipulation and readout, the quantum computers also require extremely low (cryogenic) temperatures to operate so as to preserve their coherent superposition state. The second part of this thesis presents an interface circuitry which is located on the same die and close to the quantum experiment cell. This includes key building blocks, such as digital-to-analog converters (DAC) and detectors. The proposed circuits are designed to operate at cryogenic temperatures around 4 K. They are implemented in 22-nm FDSOI CMOS from GlobalFoundries. Cryogenic test setup and off-chip controlling circuits are also presented.