Reference Oversampling for Digital Frequency Synthesis

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Title: Reference Oversampling for Digital Frequency Synthesis
Authors: Du, Jianglin
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Date: 2021
Online since: 2022-06-16T15:25:58Z
Abstract: To satisfy the strict ultra-low-power (ULP) requirements of Internet-of-Things (IoT) applications, frequency generators, as one of the most power hungry IoT blocks, must achieve high power efficiency while maintaining low phase noise (PN). The PN of frequency synthesizers is mainly determined by 1) phase detector's (PD) noise affecting in-band, and 2) oscillator's PN affecting out-of-band spectra. Traditional analog charge-pump-based phase-locked loops (PLL) face the performance degradation of PD due to the short-channel effects and limited voltage headroom of transistors in advanced technology. They also suffer from the large area occupied by bulky analog loop filters. All-digital PLLs (ADPLL) are highly compatible with the technology scaling and offer a seamless digitally intensive calibration. However, the limited linearity and resolution of a time-to-digital converter (TDC) degrades the phase noise performance. Targeting the ULP requirements in advanced CMOS technology, an oscillator of high power efficiency, and a PD of ultra-low noise in the fractional-N operation are highly sought candidates to realize RF and mm-wave frequency synthesis of high performance. In this thesis, I first propose a compact ULP 2-2.8 GHz digitally controlled oscillator (DCO), which operates at an ultra-low 0.2-0.3 V supply voltage to support energy harvesting for IoT applications. A new inverse class-F23 operation is demonstrated, which intentionally reduces the harmonics in the waveform to reduce the 1/f noise up-conversion by a proposed high magnetic-coupling (km) transformer. The upconverted phase-noise flicker (1/f3) corner reaches below 100 kHz over a 35% tuning range. Secondly, I introduce a reference-sampling all-digital PLL (RS-ADPLL) avoiding the typical power-hungry low-noise reference buffer to achieve low power and large locking range. The necessarily low time-to-voltage gain during the reference sampling is compensated by a two-stage gated amplifier which also reduces the next stage quantization noise from an ADC. By means of this digitally intensive implementation, the detector offset can be calibrated out in digital blocks. The proposed ADPLL reaches -249 dB FoMjitter with 1.1 mW power consumption. Followed by this work, I demonstrate, for the first time ever, a reference oversampling (ROS) ADPLL supporting fractional-N operation. By using a bottom-plate sampling and common-mode (CM) voltage zero-forcing technique, the proposed PD achieves a 4x reference frequency detection rate to reduce the PD noise and re-locking time under the low-power condition. The fractional-N phase is compensated with capacitive DACs controlled by a sinusoidal look-up-table (LUT) and the same DACs also preset the CM voltage for oversampling to obtain high power efficiency. The proposed 2-2.3 GHz ADPLL achieves -247 dB FoMjitter while only consuming 1.15 mW. Finally, the proposed ROS PD technique is extended to millimeter-wave (mmW) application. A novel 24--31 GHz fractional-N mmW ADPLL is introduced employing the ROS-PD. With the 4x reference frequency operation of the loop, the proposed ROS-ADPLL achieves 237 fs while using a standard 50 MHz reference frequency. Together with the class-F3 oscillator and 3rd harmonic extraction, the whole system consumes 11.5 mW leading to FoMjitter-N of -269.3 dB.
Type of material: Doctoral Thesis
Publisher: University College Dublin. School of Electrical and Electronic Engineering
Qualification Name: Ph.D.
Copyright (published version): 2021 the Author
Keywords: ADPLLOscillatorFrequency synthesisPower efficiency
Language: en
Status of Item: Peer reviewed
This item is made available under a Creative Commons License:
Appears in Collections:Electrical and Electronic Engineering Theses

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