BJT Based Precision Voltage Reference in FinFET Technology

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Title: BJT Based Precision Voltage Reference in FinFET Technology
Authors: Kamath, Umanath Ramachandra
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Date: 2021
Online since: 2022-06-16T15:33:01Z
Abstract: FinFET technology has been widely adopted for high-performance computing chips and large mixed-signal System-on-Chip (SoC). This work addresses the problem of realizing high-precision voltage references in deep nanoscale FinFET process technology. Such a problem requires consideration both at the device and circuit levels as well as their co-optimization. Hence, this thesis begins with a BJT device and its characterization in 7-nm FinFET process followed subsequently by utilizing these constructed device models for circuit realization. This work highlights the BJT device SPICE modeling and characterization results in 7-nm FinFET CMOS technology, giving special emphasis to the BJT’s variability and process spread in order to provide insights into key device-circuit interactions. This guides the optimization choices for the designer, which is crucial for analog design in deep nanoscale CMOS. BJT device characterization in 7-nm FinFET process is essential to enable not only precision voltage references, but also for other circuits such as temperature sensors, current references which use BJT at its core. Besides, the key parameters characterized helps predict the limit of achievable precision due to the underlying device inaccuracy. Subsequently, this achieves the aim of quantifying the system application performance. Measurement results of two test-chip device arrays are presented to demonstrate the feasibility of using BJTs in FinFET CMOS and the associated operating conditions (bias current density) optimal for achieving high-precision circuits. Instead of using the standard BJT layout structure available from the foundry, a merged layout structure was implemented which further saves 20% of the silicon area. This area saving layout of the BJT device could be useful for certain applications such as distributed reference or thermal sensors in large SoC. In the next part of the work, we present a 1-V precision voltage reference with a programmable temperature coefficient (‘temp-co’).The voltage reference is based on a parasitic BJT realized within the process steps available in the chosen 7-nm FinFET technology and characterized in the earlier part of this thesis. The targeted precision for this work was achieved by employing trimming techniques to manage the process spread and using two curvature compensation methods. The architecture together with these techniques ensured that the circuit was capable of handling any variation in the device models since the process technology was not mature at the time of design. In addition, the proposed architecture also is capable to program the ‘temp-co’ which is shown to be beneficial in certain applications, to compensate for any system-level thermal degradation. The reference circuit was implemented in a 7-nm TSMC FinFET technology and achieves a maximum inaccuracy of±0.2% and a minimum temp-co of 6ppm/°C from -45°C to 125°C,which is favourable in comparison to state-of-the-art voltage references. Furthermore, its temp-co is digitally programmable between -7 mV/100°C to +8 mV/100°C using a 7-bit flat-trim control code, which is an additional feature of architecture to cope with thermal gradients across large SoC by compensating system-level performance across temperature. The proposed voltage reference has a line regulation of 0.1%/V, and occupies area of 0.078 mm2.
Type of material: Doctoral Thesis
Publisher: University College Dublin. School of Electrical and Electronic Engineering
Qualification Name: Ph.D.
Copyright (published version): 2021 the Author
Keywords: BandgapBipolar junction transistor (BJT)Digitally assistedField programmable gate array
Language: en
Status of Item: Peer reviewed
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Appears in Collections:Electrical and Electronic Engineering Theses

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