Investigation of first-order digital bang-bang phase-locked loops with reference clock jitter

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Title: Investigation of first-order digital bang-bang phase-locked loops with reference clock jitter
Authors: Tertinek, Stefan
Feely, Orla
Permanent link: http://hdl.handle.net/10197/3581
Date: 16-Oct-2008
Abstract: Bang-bang phase-locked loops (BBPLLs) are a class of PLLs with a binary-quantized phase detector (BPD). They are widely used in clock and data recovery circuits and have recently been implemented as digital BBPLLs for high-bandwidth synthesis. This paper investigates a first-order digital BBPLL with reference clock jitter. We derive the Chapman-Kolmogorov equation which statistically characterizes the timing jitter process. The numerical solution of this equation allows us to compute the timing jitter probability density function (PDF) in steadystate and to examine the effect of varying loop detuning and RMS reference clock jitter on the timing offset, the RMS timing jitter and the mean number of steps to slip a cycle. The analysis shows that the steady-state PDF is Gaussian-like only for a small range of RMS clock jitter values, which leads to a new curve for the BPD gain as a function of jitter.
Funding Details: Science Foundation Ireland
Type of material: Conference Publication
Publisher: IEEE
Copyright (published version): 2008 IEEE
Keywords: Phase-locked loops;Bang-bang;Jitter
Subject LCSH: Phase-locked loops
Gaussian processes
DOI: 10.1109/NORCHP.2008.4738315
Language: en
Status of Item: Peer reviewed
Is part of: Ellervee, P., Jervan, G., Ring-Nielson, I. (eds.). 26th Norchip Conference : Tallinn, Estonia 17 - 18 November 2008 : Formal Proceedings
Conference Details: Paper presented at the Nordic microelectronics conference (NORCHIP), Tallinn, Estonia, 17-18 November, 2008
Appears in Collections:Electrical and Electronic Engineering Research Collection

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