Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops

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Title: Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops
Authors: Tertinek, Stefan
Feely, Orla
Permanent link: http://hdl.handle.net/10197/3585
Date: 24-May-2009
Abstract: Recently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional charge-pump-based analog PLLs. This paper is concerned with a class of DPLLs employing a binary-quantized phase detector, referred to as bangbang PLLs (BBPLLs). They are widely used in clock and data recovery circuits and have recently been implemented as digital BBPLLs for high-bandwidth synthesis. Given that a DPLL implementation typically suffers from (excess) loop delay, this paper investigates the combined effect of loop delay and reference clock jitter in a first-order digital BBPLL. To statistically characterize the loop’s timing jitter we formulate it as a discrete-time vector Markov process and numerically solve the associated Chapman-Kolmogorov equation. This allows us to compute the timing jitter probability density function in steady-state and to evaluate the jitter performance (timing offset and RMS timing jitter) for varying loop detuning, RMS reference clock jitter and loop delay.
Funding Details: Science Foundation Ireland
Type of material: Conference Publication
Publisher: IEEE
Copyright (published version): 2009 IEEE
Keywords: Phase-locked loops;Bang-bang;Jitter;Markov process
Subject LCSH: Phase-locked loops
Markov processes
DOI: 10.1109/ISCAS.2009.5118282
Language: en
Status of Item: Peer reviewed
Is part of: ISCAS 2009 : IEEE International Symposium on Circuits and Systems, 2009 [proceedings]
Conference Details: Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009
Appears in Collections:Electrical and Electronic Engineering Research Collection

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