Options
Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops
Author(s)
Date Issued
2009-05-24
Date Available
2012-04-24T14:55:13Z
Abstract
Recently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional
charge-pump-based analog PLLs. This paper is concerned with a class of DPLLs employing a binary-quantized phase detector, referred to as bangbang PLLs (BBPLLs). They are widely used in clock and data recovery circuits and have recently been implemented as digital BBPLLs for high-bandwidth synthesis. Given that a DPLL implementation typically suffers
from (excess) loop delay, this paper investigates the combined effect of loop delay and reference clock jitter in a first-order digital BBPLL. To statistically characterize the loop’s timing jitter we formulate it as a discrete-time vector Markov process and numerically solve the associated Chapman-Kolmogorov equation. This allows us to compute the timing jitter probability density function in steady-state and to evaluate the jitter performance (timing offset and RMS timing jitter) for varying loop detuning, RMS reference clock jitter and loop delay.
Sponsorship
Science Foundation Ireland
Type of Material
Conference Publication
Publisher
IEEE
Copyright (Published Version)
2009 IEEE
Subject – LCSH
Phase-locked loops
Markov processes
Web versions
Language
English
Status of Item
Peer reviewed
Part of
ISCAS 2009 : IEEE International Symposium on Circuits and Systems, 2009 [proceedings]
Conference Details
Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009
ISBN
978-1-4244-3827-3
This item is made available under a Creative Commons License
File(s)
Owning collection
Scopus© citations
5
Acquisition Date
Mar 28, 2024
Mar 28, 2024
Views
1453
Last Week
1
1
Last Month
1
1
Acquisition Date
Mar 28, 2024
Mar 28, 2024
Downloads
436
Last Week
2
2
Last Month
6
6
Acquisition Date
Mar 28, 2024
Mar 28, 2024