Linearized discrete-time model of higher order charge-pump PLLs
|Title:||Linearized discrete-time model of higher order charge-pump PLLs||Authors:||Bi, Chuang
Curran, Paul F.
|Permanent link:||http://hdl.handle.net/10197/3595||Date:||29-Aug-2011||Online since:||2012-05-01T11:44:50Z||Abstract:||In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs). The behaviour of CP-PLLs in the steady state is analysed and an important feature is developed. The nonlinear state equations of CP-PLLs are linearized around the equilibrium point. The linearized discrete-time model is finally verified using behavioral simulations in Matlab and PSpice.||Funding Details:||Science Foundation Ireland||Type of material:||Conference Publication||Publisher:||IEEE||Copyright (published version):||2011 IEEE||Keywords:||Phase-locked loops; Charge-pump||Subject LCSH:||Phase-locked loops
On-chip charge pumps
|DOI:||10.1109/ECCTD.2011.6043385||Other versions:||http://dx.doi.org/10.1109/ECCTD.2011.6043385||Language:||en||Status of Item:||Peer reviewed||Is part of:||2011 20th European Conference on Circuit Theory and Design (ECCTD) [proceedings]||Conference Details:||European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, 29-31 August, 2011||ISBN:||978-1-4577-0617-2|
|Appears in Collections:||Electrical and Electronic Engineering Research Collection|
Show full item record
Page view(s) 20158
This item is available under the Attribution-NonCommercial-NoDerivs 3.0 Ireland. No item may be reproduced for commercial purposes. For other possible restrictions on use please refer to the publisher's URL where this is made available, or to notes contained in the item itself. Other terms may apply.