Limit Cycle Behavior in a Class-AB Second-Order Square Root Domain Filter
|Title:||Limit Cycle Behavior in a Class-AB Second-Order Square Root Domain Filter||Authors:||De La Cruz Blas, Carlos A.
|Permanent link:||http://hdl.handle.net/10197/3741||Date:||Aug-2011||Abstract:||This paper shows how an unwanted limit cycle can be exhibited by a second-order CMOS companding filter. The filter employs the quasi-quadratic law of the MOS transistor in strong inversion and saturation to achieve compression together with a Class-AB topology to extend the dynamic range. In the zero-input case, the filter operates in the manner expected of an externally-linear circuit. However, when a standard linear IC design technique is applied to it, unwanted zero-input sustained oscillations may be observed. Simulations from PSpice and measurement results from a semi-custom realization in a 0.8μm CMOS process are used to explore this behavior. This work highlights an aspect of the behavior of such filters that must be taken into account by analog designers.||Funding Details:||Science Foundation Ireland||Type of material:||Journal Article||Publisher:||Springer||Journal:||Analog Integrated Circuits and Signal Processing||Volume:||68||Issue:||2||Start page:||171||End page:||181||Copyright (published version):||2011 Springer||Keywords:||Square root domain; Log domain; Filters||Subject LCSH:||Log domain filters
|DOI:||10.1007/s10470-011-9599-4||Language:||en||Status of Item:||Peer reviewed|
|Appears in Collections:||Electrical and Electronic Engineering Research Collection|
Show full item record
Page view(s) 5098
This item is available under the Attribution-NonCommercial-NoDerivs 3.0 Ireland. No item may be reproduced for commercial purposes. For other possible restrictions on use please refer to the publisher's URL where this is made available, or to notes contained in the item itself. Other terms may apply.