Exploiting Multi-Core Architectures for Reduced-Variance Estimation with Intractable Likelihoods

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Title: Exploiting Multi-Core Architectures for Reduced-Variance Estimation with Intractable Likelihoods
Authors: Friel, Nial
Mira, Antonietta
Oates, Chris J.
Permanent link: http://hdl.handle.net/10197/6729
Date: 2015
Online since: 2015-08-05T16:24:56Z
Abstract: Many popular statistical models for complex phenomena areintractable, in the sense that the likelihood function cannot easily be evaluated.Bayesian estimation in this setting remains challenging, with a lack of computa-tional methodology to fully exploit modern processing capabilities. In this paperwe introduce novel control variates for intractable likelihoods that can dramati-cally reduce the Monte Carlo variance of Bayesian estimators. We prove that ourcontrol variates are well-defined and provide a positive variance reduction. Fur-thermore, we show how to optimise these control variates for variance reduction.The methodology is highly parallel and offers a route to exploit multi-core pro-cessing architectures that complements recent research in this direction. Indeed,our work shows that it may not be necessary to parallelise the sampling processitself in order to harness the potential of massively multi-core architectures. Simu-lation results presented on the Ising model, exponential random graph models andnon-linear stochastic differential equation models support our theoretical findings.
Funding Details: Science Foundation Ireland
Type of material: Journal Article
Publisher: International Society for Bayesian Analysis (ISBA)
Journal: Bayesian Analysis
Volume: 11
Issue: 1
Start page: 1
End page: 31
Copyright (published version): 2015 International Society for Bayesian Analysis
Keywords: Machine learningStatisticsControl variatesMCMCParallel computingZero variance
DOI: 10.1214/15-BA948
Language: en
Status of Item: Peer reviewed
Appears in Collections:Mathematics and Statistics Research Collection
Insight Research Collection

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