SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing

Title: SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing
Authors: Patel, Kunjan
McGettrick, Séamas
Bleakley, Chris J.
Permanent link: http://hdl.handle.net/10197/7033
Date: 3-May-2011
Abstract: The promise of 24/7 patient monitoring and online diagnosis using wearable and implantable biomedical devices has engendered significant research interest in the development of low power biosignal processing platforms. Herein, a novel Coarse Grained Reconfigurable Array (CGRA) architecture is presented for low power, real time processing of biomedical signals. The proposed architecture differs from previously proposed CGRAs in that it is designed for low power, rather than for high performance. The proposed architecture was implemented in a software modeler and simulator and in Verilog. The architecture was shown to provide savings in energy consumption of up to 99% and speed up of up to 64 times compared to a conventional DSP processor for typical biosignal processing functions.
Funding Details: Science Foundation Ireland
Type of material: Conference Publication
Publisher: IEEE
Copyright (published version): 2011 IEEE
Keywords: Coarse grained reconfigurable architecture;Systolic;Low energy;Biosignal
DOI: 10.1109/FCCM.2011.38
Language: en
Status of Item: Peer reviewed
Conference Details: 19th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Salt Lake City, Utah, USA, 1 - 3 May, 2011
Appears in Collections:Computer Science Research Collection
CASL Research Collection

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