Reliability Analysis of Memories Protected with BICS and a per-Word Parity Bit
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|Title:||Reliability Analysis of Memories Protected with BICS and a per-Word Parity Bit||Authors:||Reviriego, P.
Bleakley, Chris J.
|Permanent link:||http://hdl.handle.net/10197/7063||Date:||Feb-2010||Abstract:||This paper presents an analysis of the reliability of memories protected with Built-in Current Sensors (BICS) and a per-word parity bit when exposed to Single Event Upsets (SEUs). Reliability is characterized by Mean Time to Failure (MTTF) for which two analytic models are proposed. A simple model, similar to the one traditionally used for memories protected with scrubbing, is proposed for the low error rate case. A more complex Markov model is proposed for the high error rate case. The accuracy of the models is checked using a wide set of simulations. The results presented in this paper allow fast estimation of MTTF enabling design of optimal memory configurations to meet specified MTTF goals at minimum cost. Additionally the power consumption of memories protected with BICS is compared to that of memories using scrubbing in terms of the number of read cycles needed in both configurations.||Type of material:||Journal Article||Publisher:||Association for Computing Machinery (ACM)||Journal:||ACM Transactions on Design Automation of Electronic Systems||Volume:||15||Issue:||2||Start page:||18.1||End page:||18.15||Copyright (published version):||2010 ACM||Keywords:||Design; Reliability; Fault-tolerant memory; Error correcting codes; High-level protection technique; Built-in current sensors||DOI:||10.1145/1698759.1698768||Language:||en||Status of Item:||Peer reviewed|
|Appears in Collections:||Computer Science Research Collection|
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