Low Complexity Concurrent Error Detection for Complex Multiplication

Files in This Item:
File Description SizeFormat 
Low_Complexity_Concurrent_Error_Detection_for_Complex_Multiplication.pdf300.65 kBAdobe PDFDownload
Title: Low Complexity Concurrent Error Detection for Complex Multiplication
Authors: Pontarelli, Salvatore
Reviriego, P.
Bleakley, Chris J.
Maestro, J.A.
Permanent link: http://hdl.handle.net/10197/7090
Date: Sep-2013
Abstract: This paper studies the problem of designing a low complexity Concurrent Error Detection (CED) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits. Five novel CED architectures are proposed and their computational complexity, area, and delay evaluated in several circuit implementations. The most efficient architecture proposed reduces the number of gates required by up to 30 percent when compared with a conventional CED architecture based on Dual Modular Redundancy. Compared to a Residue Code CED scheme, the area of the proposed architectures is larger. However, for some of the proposed CEDs delay is significantly lower with reductions exceeding 30 percent in some configurations.
Type of material: Journal Article
Publisher: IEEE
Copyright (published version): 2013 IEEE
Keywords: Complex multiplicationConcurrent error detectionFault tolerance
DOI: 10.1109/TC.2012.246
Language: en
Status of Item: Peer reviewed
Appears in Collections:Computer Science Research Collection

Show full item record

Citations 50

Last Week
Last month
checked on Aug 17, 2018

Download(s) 50

checked on May 25, 2018

Google ScholarTM



This item is available under the Attribution-NonCommercial-NoDerivs 3.0 Ireland. No item may be reproduced for commercial purposes. For other possible restrictions on use please refer to the publisher's URL where this is made available, or to notes contained in the item itself. Other terms may apply.