GALS SoC Interconnect Bus for Wireless Sensor Network Processor Platforms
Files in This Item:
|GALS_SoC_Interconnect_Bus_for_Wireless_Sensor_Network_Processor_Platforms.pdf||251.74 kB||Adobe PDF||Download|
|Title:||GALS SoC Interconnect Bus for Wireless Sensor Network Processor Platforms||Authors:||Fernandez, Carlos H.
Raval, Rajkumar K.
Bleakley, Chris J.
|Permanent link:||http://hdl.handle.net/10197/7112||Date:||13-Mar-2007||Abstract:||The purpose of this paper is to present a new System-on-Chip bus designed for the application specific requirements of Wireless Sensor Network (WSN) platforms. The bus is designed to support Globally Asynchronous Locally Synchronous (GALS) systems. The bus is multi-rate with delay tolerance to support Dynamic Voltage and Frequency Scaled (DVFS) sub-systems. Unlike traditional buses, the sub-systems operate as peers, rather than as master-slaves. Lowpower features include clock gating when inactive and burst transfers. The bus supports up to 255 interconnected resources.||Type of material:||Conference Publication||Publisher:||Association for Computing Machinery||Copyright (published version):||2007 ACM||Keywords:||Design;Wireless sensor network;WSN;System on Chip bus;SoC bus;Low power;Application specific bus;GALS||DOI:||10.1145/1228784.1228819||Language:||en||Status of Item:||Peer reviewed||Conference Details:||Proceedings of the 17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stressa-Lago Maggiore, Italy, 11 - 13 March, 2007|
|Appears in Collections:||Computer Science Research Collection|
Show full item record
This item is available under the Attribution-NonCommercial-NoDerivs 3.0 Ireland. No item may be reproduced for commercial purposes. For other possible restrictions on use please refer to the publisher's URL where this is made available, or to notes contained in the item itself. Other terms may apply.