GALS SoC Interconnect Bus for Wireless Sensor Network Processor Platforms

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Title: GALS SoC Interconnect Bus for Wireless Sensor Network Processor Platforms
Authors: Fernandez, Carlos H.
Raval, Rajkumar K.
Bleakley, Chris J.
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Date: 13-Mar-2007
Online since: 2015-09-25T12:13:04Z
Abstract: The purpose of this paper is to present a new System-on-Chip bus designed for the application specific requirements of Wireless Sensor Network (WSN) platforms. The bus is designed to support Globally Asynchronous Locally Synchronous (GALS) systems. The bus is multi-rate with delay tolerance to support Dynamic Voltage and Frequency Scaled (DVFS) sub-systems. Unlike traditional buses, the sub-systems operate as peers, rather than as master-slaves. Lowpower features include clock gating when inactive and burst transfers. The bus supports up to 255 interconnected resources.
Type of material: Conference Publication
Publisher: Association for Computing Machinery
Copyright (published version): 2007 ACM
Keywords: DesignWireless sensor networkWSNSystem on Chip busSoC busLow powerApplication specific busGALS
DOI: 10.1145/1228784.1228819
Language: en
Status of Item: Peer reviewed
Conference Details: Proceedings of the 17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stressa-Lago Maggiore, Italy, 11 - 13 March, 2007
Appears in Collections:Computer Science Research Collection

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