A DSP Coprocessor for ADSL Lite

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Title: A DSP Coprocessor for ADSL Lite
Authors: Berg, Vincent
Rodriguez, Jose
Bleakley, Chris J.
Murray, Brian
Permanent link: http://hdl.handle.net/10197/7117
Date: Jan-1999
Online since: 2015-09-25T14:34:18Z
Abstract: This paper presents Massana's DSP co-processor solution – FILU-DMT [1] for enabling soft G.Lite (or ADSL Lite) on Pentium and RISC processors. The user interacts with the coprocessor via a C API which accesses a shared RAM interface. All of the G.Lite DSP functions are pre-programmed and held in ROM. The FILU-DMT is implemented in fully synthesizable Verilog RTL with a single synchronous clock for high scan coverage. It is based on a dual MAC architecture which can perform a radix-4 FFT butterfly in 8 cycles yielding a 256 point FFT in 21 µs. This is the industry's fastest FFT for this class of processor. The FILU-DMT supports block floating-point arithmetic which achieves near floating-point performance at a fraction of the area cost of conventional DSPs.
Type of material: Conference Publication
Keywords: Very-large-scale integration (VLSI)Digital signal processingDigital Subscriber Line (DSL)
Other versions: http://www.cs.ucd.ie/staff/cbleakley/home/papers/issc99_paper.pdf
Language: en
Status of Item: Peer reviewed
Conference Details: Irish Signals and Systems Conference (ISSC), Galway, Ireland, January, 1999
Appears in Collections:Computer Science Research Collection

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