A DSP Coprocessor for ADSL Lite

Files in This Item:
File Description SizeFormat 
A_DSP_Co-processor_Core_for_ADSL_Lite.pdf155.45 kBAdobe PDFDownload
Title: A DSP Coprocessor for ADSL Lite
Authors: Berg, Vincent
Rodriguez, Jose
Bleakley, Chris J.
Murray, Brian
Permanent link: http://hdl.handle.net/10197/7117
Date: Jan-1999
Abstract: This paper presents Massana's DSP co-processor solution – FILU-DMT [1] for enabling soft G.Lite (or ADSL Lite) on Pentium and RISC processors. The user interacts with the coprocessor via a C API which accesses a shared RAM interface. All of the G.Lite DSP functions are pre-programmed and held in ROM. The FILU-DMT is implemented in fully synthesizable Verilog RTL with a single synchronous clock for high scan coverage. It is based on a dual MAC architecture which can perform a radix-4 FFT butterfly in 8 cycles yielding a 256 point FFT in 21 µs. This is the industry's fastest FFT for this class of processor. The FILU-DMT supports block floating-point arithmetic which achieves near floating-point performance at a fraction of the area cost of conventional DSPs.
Type of material: Conference Publication
Keywords: Very-large-scale integration (VLSI);Digital signal processing;Digital Subscriber Line (DSL)
Language: en
Status of Item: Peer reviewed
Conference Details: Irish Signals and Systems Conference (ISSC), Galway, Ireland, January, 1999
Appears in Collections:Computer Science Research Collection

Show full item record

Download(s) 50

49
checked on May 25, 2018

Google ScholarTM

Check


This item is available under the Attribution-NonCommercial-NoDerivs 3.0 Ireland. No item may be reproduced for commercial purposes. For other possible restrictions on use please refer to the publisher's URL where this is made available, or to notes contained in the item itself. Other terms may apply.