Low-Power TinyOS Tuned Processor Platform for Wireless Sensor Network Motes
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|Title:||Low-Power TinyOS Tuned Processor Platform for Wireless Sensor Network Motes||Authors:||Raval, Rajkumar K.
Fernandez, Carlos H.
Bleakley, Chris J.
|Permanent link:||http://hdl.handle.net/10197/7123||Date:||3-May-2010||Abstract:||In this article we describe a low power processor platform for use in Wireless Sensor Network (WSN) nodes (motes). WSN motes are small, battery-powered devices comprised of a processor, sensors, and a Radio Frequency transceiver. It is expected that WSNs consisting of large numbers of motes will offer long-term, distributed monitoring, and control of real-world equipment and phenomena. A key requirement for these applications is long battery life. We investigate a processor platform architecture based on an application-specific programmable processor core, System-On-Chip bus, and a hardware accelerator. The architecture improves on the energy consumption of a conventional microprocessor design by tuning the architecture for a suite of TinyOS based WSN applications. The tuning method used minimizes changes to the Instruction Set Architecture facilitating rapid software migration to the new platform. The processor platform was implemented and validated in an FPGA-based WSN mote. The benefits of the approach in terms of energy consumption are estimated to be a reduction of 48% for ASIC implementation relative to a conventional programmable processor for a typical TinyOS application suite without use of voltage scaling.||Funding Details:||Enterprise Ireland
Science Foundation Ireland
|Type of material:||Journal Article||Publisher:||Association for Computing Machinery (ACM)||Copyright (published version):||2010 ACM||Keywords:||Embedded system design;Hardware-software co-design;Wireless Sensor Network;Low power processor||DOI:||10.1145/1754405.1754408||Language:||en||Status of Item:||Peer reviewed|
|Appears in Collections:||Computer Science Research Collection|
CASL Research Collection
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